Semiconductor memory device with redundant memory cells

Details Semiconductor memory device with redundant memory cells Semiconductor memory device with redundant memory cells

2003-01-27

2004-05-18

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700, C365S230060

Reexamination Certificate

active

06738299

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device equipped with a circuit configuration for replacing defective memory cells with redundant memory cells.
To compensate for defective memory cells in a semiconductor memory device, there has been known a technique whereby spare memory cells (hereinafter referred to as “redundant cells”) are provided in the semiconductor memory device so as to replace a memory cell that has incurred failure with a redundant cell. As a means for substituting a redundant cell for a defective memory cell, an electric circuit (hereinafter referred to as “the redundancy circuit”) is usually used.
For example, there is a redundancy system known as “shift redundancy.” According to this system, a decoder output terminal is connected to a certain selector line through the intermediary of a switching circuit. If a defective memory cell is found, the connection to the selector line connected with the defective memory cell is shifted to the selector line connected to a non-defective memory cell, and a selection signal is transmitted.
With the progress in the microprocessing technology in the manufacture of semiconductor devices, the trend toward enhanced microprocessing in the manufacture of semiconductor memory devices is accelerating. A redundancy circuit for replacing defective memory cells is an essential part for improving a yield by compensating for defective memory cells, which are inevitably produced during a manufacturing process. However, the size of the fuses suitably used with the redundancy circuit depends on the machining process of a laser, making it virtually difficult to miniaturize the fuse to catch up with the increasing miniaturization of memory cells.
More specifically, in a configuration wherein a plurality of fuses are connected in series, if the pitch of a decoder, that is, the pitch of a memory cell is larger than the pitch of a fuse, then there should be no problem. If, however, the pitch of memory cells become further smaller with the increasing trend toward enhanced microprocessing in the manufacture, the number of the rows of memory cells that can be replaced by one fuse will be two or more. Hence, even when replacing just one row of memory cells would be adequate to compensate for defective memory cells, two or more rows of memory cells would have to be replaced. This would require two or more rows of redundant memory cells be prepared for replacing a single defective memory cell. As a result, the area occupied by the fuses in the redundancy circuit and the area occupied by the increased number of redundant memory cells will lead to a larger chip area.
To access a particular memory cell, an X address thereof is first input, and it is determined whether the memory cell associated with the address need to be replaced by a redundant memory cell, then the X address is defined. Thereafter, a Y address is input, and the Y address is defined, then data is input or output in relation to the memory cell.
Thus, in order to secure a high-speed operation of a semiconductor memory while carrying out redundancy replacement, it is necessary to start the switching for a Y address when an X address is defined, and to complete the switching operation before the Y address is input.
SUMMARY OF THE INVENTION
Accordingly, the present invention may provide a semiconductor memory device equipped with a redundant memory cell for replacing a defective memory cell.
A semiconductor memory device according to the present invention includes a redundancy circuit having predecode signal lines, a fuse predecode circuit, fuse decode circuit and an address decode circuit. The fuse predecode circuit is connected to the fuse predecode signal lines. The fuse predecode circuit includes drivers each of which generates a drive signal in response to one of first address signals received by the fuse predecode circuit. The fuse predecode circuit further includes terminal circuits connected to the predecode signal lines for latching signals appeared thereon, and fuse circuits each of which is connected between one of the predecode signal lines and a first potential source. Each of the fuse circuits includes a transistor having a control terminal connected to one of the drivers and a fuse connected to the transistor in series.


REFERENCES:
patent: 5469391 (1995-11-01), Haraguchi
patent: 11213688 (1999-06-01), None

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