Semiconductor memory device with redundant memory cells

Details Semiconductor memory device with redundant memory cells Semiconductor memory device with redundant memory cells

1989-01-19

1990-06-19

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, G11C 700

Patent

active

049358995

ABSTRACT:
In a semiconductor memory device with a redundant memory cell array provided in association with a memory cell array partially replacable with the redundant memory cells, each programming circuit has a conduction path flowing a current in the absence of a defective memory cell for shifting a redundant memory controller into an inactive state, a redundant memory activation circuit produces an enable signal in the presence of the detective memory cell for shifting the controller into an active state and further produces a disenable signal in the absence of the defective memory cell, and a blocking transistor is provided in the conduction path and responsive to the disenable signal to block the conduction path, thereby causing the amount of current consumed to be decreased.

REFERENCES:
patent: 4720817 (1988-01-01), Childers
patent: 4731759 (1988-03-01), Watanabe

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