Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1996-12-23
1998-07-21
Zarabian, A.
Static information storage and retrieval
Read/write circuit
Bad bit
365201, G11C 700
Patent
active
057843210
ABSTRACT:
A semiconductor memory device in a semiconductor memory circuit with a redundant memory, in which a redundant memory cell compulsory selection circuit is provided and a redundant memory cell compulsory selection signal and a redundant memory address are given from an external portion, whereby after performing the inspection of the redundant memory cell array in advance, the defective row or defective column of the normal memory cell array can be set to a position of the redundant memory cell array not including a defect.
REFERENCES:
patent: 5430678 (1995-07-01), Tomita
patent: 5523974 (1996-06-01), Hirano
patent: 5539698 (1996-07-01), Suzuki
patent: 5555212 (1996-09-01), Toshiaki
patent: 5561632 (1996-10-01), Arase
Kananen Ronald P.
Sony Corporation
Zarabian A.
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