Semiconductor memory device with redundancy circuit

Details Semiconductor memory device with redundancy circuit Semiconductor memory device with redundancy circuit

1994-09-12

1996-05-14

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523003, G11C 700

Patent

active

055174507

ABSTRACT:
A semiconductor memory device includes a memory cell array divided into a plurality of blocks, the row of memory cells is selected by a row selection circuit, and the column of the memory cells is selected by a column selection circuit for the plurality of blocks. Spare memory cells are respectively provided for the plurality of blocks and the spare memory cell is selected for each block by a spare column selection circuit. When a defective memory cell is contained in the memory cells, the defective memory cell is replaced by the spare memory cell for each block unit by use of a replacing circuit. A selection controlling circuit controls the row selection circuit to simultaneously activate at least two blocks. When defects are present in at least two blocks which are simultaneously activated, selection of the blocks which are simultaneously activated is changed by a changing circuit.

REFERENCES:
patent: 4935899 (1990-06-01), Morigami
patent: 5272672 (1993-12-01), Ogihara
patent: 5357470 (1994-10-01), Namekawa
IEEE Journal of Solid-State Circuits, "A 45-ns 16-Mbit DRAM with Triple-Well Structure", vol. 24, No. 5, Oct. 1989, pp. 1170-1175.

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