Semiconductor memory device with redundancy circuit

Details Semiconductor memory device with redundancy circuit Semiconductor memory device with redundancy circuit

1992-10-08

1994-02-22

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, 36523006, 371 103, G11C 2900

Patent

active

052894177

ABSTRACT:
A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.

REFERENCES:
patent: 4365319 (1982-12-01), Takemae
patent: 4879687 (1989-11-01), Okamoto et al.
patent: 4908798 (1990-03-01), Urai
patent: 4918662 (1990-04-01), Kondo
patent: 4998223 (1991-03-01), Akaogi

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