Semiconductor memory device with reduced skew on data line

Details Semiconductor memory device with reduced skew on data line Semiconductor memory device with reduced skew on data line

2007-03-27

2007-03-27

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S189050

Reexamination Certificate

active

11019190

ABSTRACT:
A semiconductor memory device including: a plurality of read sense amplifiers for amplifying an output data of a memory cell; a plurality of read delay controllers for delaying an output data of the read sense amplifier by a predetermined time; a plurality of read latches for outputting an output data of the read delay controller as an external data in response to a read strobe signal; a plurality of write sense amplifiers for sensing and amplifying the external data in response to a write strobe signal; a plurality of write delay controllers for delaying an output data of the write sense amplifier by a predetermined time; a plurality of write drivers for inputting an output data of the write delay controller to the memory cell in response to a write enable signal; and a plurality of data buses for transferring the data.

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