Semiconductor memory device with reduced probability of power co

Details Semiconductor memory device with reduced probability of power co Semiconductor memory device with reduced probability of power co

1996-07-19

1998-07-28

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Semiconductive

365104, G11C 1710

Patent

active

057870330

ABSTRACT:
A programming of memory cells in an upper block (UB) is reversely made, thereby obtaining reverse data which are opposite to desired data when the upper block (UB) is selected. An inverter circuit (IV) is additionally provided at an output of a sense amplifier (SA1) and inverts the reverse data, thus eventually obtaining the desired data. Having such configuration as to reduce the number of ON/OFF controllable memory cells, a semiconductor memory device which cuts power consumption is provided. Moreover, with OFF-state memory cells having such configuration as to suppress application of load (charge) capacity to bit lines and word lines as much as possible, the semiconductor memory device which ensures high-speed access to the memory cells is provided.

REFERENCES:
patent: 5477484 (1995-12-01), Nakashima

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