Semiconductor memory device with reduced power consumption and s

Details Semiconductor memory device with reduced power consumption and s Semiconductor memory device with reduced power consumption and s

1998-03-16

2000-02-15

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Data refresh

36518525, 36518911, G11C 1124

Patent

active

060260432

ABSTRACT:
The semiconductor memory device has a normal operation mode and a self-refresh mode, and includes a V.sub.BB generation circuit generating a first substrate voltage when an internal power supply voltage is larger than a predetermined value and a second substrate voltage of an absolute value smaller than that of the first substrate voltage when V.sub.CC is smaller than the predetermined value, a bit line equivalent voltage generation circuit outputting voltage V.sub.CC /2 produced by resistive dividing when internal power supply voltage is lower than the predetermined value in self-refresh mode, a 4KE signal generation circuit generating a signal for performing a 4K operation in the self-refresh mode when internal power supply voltage is lower than the predetermined value and a refresh address generation circuit.

REFERENCES:
patent: 5694365 (1997-12-01), Nakai
patent: 5699303 (1997-12-01), Hamamoto et al.
patent: 5712825 (1998-01-01), Hadderman
patent: 5822264 (1998-10-01), Tomishima
patent: 5841705 (1998-11-01), Hamamoto et al.
patent: 5867438 (1999-02-01), Nomura et al.
patent: 5877978 (1999-03-01), Morishita et al.

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