Semiconductor memory device with reduced power consumption...

Details Semiconductor memory device with reduced power consumption... Semiconductor memory device with reduced power consumption...

2001-11-16

2003-01-07

Lam, David (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C365S222000, C365S194000

Reexamination Certificate

active

06504787

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a dynamic random access memory (DRAM) that allows reduction in power consumption during a refresh operation.
2. Description of the Background Art
FIG. 15
is a block diagram representing an arrangement of a control circuit
508
for performing a role activation timing control in a conventional synchronous DRAM.
Referring to
FIG. 15
, control circuit
508
receives control signals int.ZRAS, int.ZCAS, int.ZWE, and int.ZCS and internal bank address signals int.BA<
0
:
1
>, and outputs row address decode signals RADE<
0
:
3
>, word line trigger signals RXT<
0
:
3
>, sense amplifier activating signals S
0
N<
0
:
3
>, and an internal address Q for refresh operation. In addition, a prefix “Z” indicates that the signal is an L-active signal, i.e. a signal whose active state is at the low level.
Control circuit
508
includes a command decode circuit
552
for receiving control signals int.ZRAS, int. ZCAS, int.ZWE, and int.ZCS and detecting a command from a combination of these signals, and a refresh control unit
554
for performing refresh control according to an output from command decode circuit
552
.
Control circuit
508
further includes a bank selecting unit
556
for selecting the output of command decode circuit
552
according to internal bank address signals int.BA<
0
:
1
>, and a bank selecting unit
560
for selecting an output of refresh control unit
554
according to internal bank address signals int.BA<
0
:
1
>.
Control circuit
508
further includes an NOR circuit
558
for receiving signals ACT<
0
:
3
> output from bank selecting unit
556
and signals AREF<
0
:
3
> output from bank selecting unit
560
and outputting signals ZRASE<
0
:
3
>, and a control circuit
562
for outputting row address decode signals RADE<
0
:
3
>, word line trigger signals RXT<
0
:
3
>, and sense amplifier activating signals S
0
N<
0
:
3
> according to signals AREF<
0
:
3
> and signals ZRASE<
0
:
3
>.
Command decode circuit
552
includes an active command decoder
572
for receiving control signals int.ZRAS, int.ZCAS, int.ZWE, and int.ZCS to detect an active command, an auto-refresh command decoder
574
for receiving control signals int.ZRAS, int.ZCAS, int.ZWE, and int.ZCS to detect an auto-refresh command, and a self-refresh command decoder
576
for receiving control signals int.ZRAS, int.ZCAS, int.ZWE, and int.ZCS to detect a self-refresh command.
Refresh control unit
554
includes a self-refresh timer
580
for activating a signal RINGOUT at certain intervals according to a signal SREF output from self-refresh command decoder
576
, a refresh operation control circuit
582
for outputting a signal AREFS according to an output from auto-refresh command decoder
574
and a signal RINGOUT, a 1 shot pulse generating circuit
584
for outputting a signal REFA according to signal AREFS, and an internal address counter
586
for counting internal address Q during a refresh operation according to signal REFA.
Control circuit
562
includes a row-related control circuit
564
for outputting a row address decode signal RADE<
0
>, a word line trigger signal RXT<
0
>, and a sense amplifier activating signal S
0
N<
0
> according to a signal ZRASE<
0
>, a row-related control circuit
566
for outputting a row address decode signal RADE<
1
>, a word line trigger signal RXT<
1
>, and a sense amplifier activating signal S
0
N<
1
> according to a signal ZRASE<
1
>, a row-related control circuit
568
for outputting a row address decode signal RADE<
2
>, a word line trigger signal RXT<
2
>, and a sense amplifier activating signal S
0
N<
2
> according to a signal ZRASE<
2
>, and a row-related control circuit
570
for outputting a row address decode signal RADE<
3
>, a word line trigger signal RXT<
3
>, and a sense amplifier activating signal S
0
N<
3
> according to a signal ZRASE<
3
>.
FIG. 16
is a circuit diagram showing an arrangement of row-related control circuit
564
in FIG.
15
.
Referring to
FIG. 16
, row-related control circuit
564
includes a signal generating unit
632
for outputting a row address decode signal RADE according to a signal ZRASE, a signal generating unit
634
for outputting a signal RXT according to a signal ZRASE and signal RADE, and a signal generating unit
636
for outputting sense amplifier activating signals S
0
N, /S
0
N according to signal RXT.
Signal generating unit
632
includes a delay stage
640
for delaying sense amplifier activating signal S
0
N, an inverter
638
for receiving and inverting signal ZRASE, and an OR circuit
642
for receiving outputs from delay stage
640
and inverter
638
and outputting signal RADE.
Delay stage
640
includes inverters
644
and
646
connected in series for receiving sense amplifier activating signal S
0
N.
Signal generating unit
634
includes an inverter
648
for receiving and inverting signal ZRASE, a delay stage
650
for receiving and delaying an output from inverter
648
, a delay stage
652
for delaying signal RADE, and an AND circuit
654
for receiving outputs from delay stages
650
and
652
and outputting signal RXT.
Delay stage
650
includes inverters
656
and
658
connected in series for receiving the output from inverter
648
. Delay stage
652
includes inverters
660
and
662
connected in series for receiving signal RADE.
Signal generating unit
636
includes a delay stage
664
for receiving and delaying signal RXT and outputting sense amplifier activating signal S
0
N, and an inverter
676
for receiving and inverting sense amplifier activating signal S
0
N and outputting sense amplifier activating signal /S
0
N.
Delay stage
664
includes inverters
678
and
680
connected in series for receiving signal RXT.
FIG. 17
is a circuit diagram representing the arrangement of auto-refresh command decoder
574
and refresh operation control circuit
582
in FIG.
15
.
Referring to
FIG. 17
, auto-refresh command decoder
574
includes an inverter
692
for receiving and inverting a signal int.ZRAS, an inverter
694
for receiving and inverting a signal int.ZCAS, and an NAND circuit
696
for receiving outputs from inverters
692
and
694
and a signal int.ZWE.
Refresh operation control circuit
582
receives an output from NAND circuit
696
at a node N
11
.
Refresh operation control circuit
582
includes an inversion delay circuit
698
having an input connected to node N
11
and an output connected to a node N
13
, an NOR circuit
700
having one input connected to node N
11
, the other input connected to node N
13
, and an output connected to a node N
12
, and an NOR circuit
702
for receiving signal RINGOUT and an output from NOR circuit
700
. Inversion delay circuit
698
includes inverters
710
,
712
, and
714
connected in series.
Refresh operation control circuit
582
further includes a latch circuit
704
having the data set according to an output of NOR circuit
702
, a delay stage
706
for delaying an output from latch circuit
704
, and an inverter
708
for inverting an output from delay stage
706
.
Latch circuit
704
includes an NAND circuit
716
having one input receiving the output from NOR circuit
702
and the other input connected to a node N
15
for outputting a signal AREFS, and an NAND circuit
718
having one input receiving signal AREFS, the other input connected to a node N
14
, and an output node connected to node N
15
.
Delay stage
706
includes inverters
720
and
722
connected in series for receiving signal AREFS.
FIG. 18
is an operational waveform chart related to a description of an auto-refresh operation of a conventional DRAM.
Referring to
FIG. 18
, signals ext.ZRAS, ext.ZCAS, ext.ZWE, CKE, ext.CLK, and ext.ZCS are input signals externally supplied to the DRAM. A signal ext.ZRAS is row address strobe signal, and a signal ext.ZCAS

Affiliated with

Also associated with

Rating

Semiconductor memory device with reduced power consumption... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device with reduced power consumption..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with reduced power consumption... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3003105