Semiconductor memory device with reduced memory cell area

Details Semiconductor memory device with reduced memory cell area Semiconductor memory device with reduced memory cell area

2005-08-30

2005-08-30

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S303000, C257S306000, C257S315000, C257S903000

Reexamination Certificate

active

06936878

ABSTRACT:
A semiconductor memory device includes a memory cell, and first and second capacitive elements. The memory cell has a pair of inverters each including first and second driver nMOS transistors and first and second TFTs, and first and second access nMQS transistors. The first and second capacitive elements is connected to the drain of first and second access nMOS transistors, the drain of first and second driver nMOS transistors, and the drain of first and second TFTs. The gate width of first and second driver nMOS transistors is set at most 1.2 times longer than the gate width of first and second access nMOS transistors.

REFERENCES:
patent: 6479860 (2002-11-01), Ohbayashi
patent: 62-257698 (1987-11-01), None
patent: 6-291281 (1994-10-01), None
patent: 7-161840 (1995-06-01), None
Naiki, et al. “Center Wordline Cell: A New Symmetric Layout Cell for 64Mb SRAM” International Electron Devices Meeting Technical Digest, Washington, D.C. (Dec. 5-8, 1993) pp. 33.3.1-33.3.4.

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