Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1996-12-16
1998-08-25
Hoang, Huan
Static information storage and retrieval
Read/write circuit
Data refresh
36523003, 365226, G11C 700
Patent
active
057989761
ABSTRACT:
In a normal operation mode, a dynamic random access memory DRAM has a plurality of memory mats simultaneously selected. During a refresh operation, refreshing is effected simultaneously on a plurality of memory sub-arrays in one of the memory mats. A control signal only for one memory mat is required to be driven, so that a current consumption in a data holding mode can be reduced. Further, by reducing a circuit operation speed, a peak current can be reduced.
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Yoshimoto, Masahiko, et al: "A 64Kb Full CMOS RAM with Divided word Line Structure", 1983 IEEE International Solid-State Circuit Conference, pp. 58-59. No Month.
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Kitsukawa, Goro, et al: "256Mb DRAM Technologies for File Applications", 1993 IEEE International Solid-State Circuits Conference, pp. 48-49. No Month.
Hoang Huan
Mitsubishi Denki & Kabushiki Kaisha
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