Semiconductor memory device with reduced current consumption...

Details Semiconductor memory device with reduced current consumption... Semiconductor memory device with reduced current consumption...

2000-02-23

2002-07-30

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S226000, C365S229000

Reexamination Certificate

active

06426908

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices, and in particular to configurations for reducing the current consumed in a refresh mode for holding data, such as a sleep mode or a power down mode, without causing an erroneous operation in a semiconductor memory device requiring refreshing of storage data. More specifically, the present invention relates to a configuration for reducing the current consumed in a refresh mode by a logic merged memory with a logic and a dynamic random access memory integrated on a single semiconductor chip.
2. Description of the Background Art
A conventional CMOS semiconductor device is reduced in transistor size, in particular, gate length of a MOS transistor (an insulated gate field effect transistor) to achieve high density and high integration. While a reduced power supply voltage is employed to ensure the reliability of such a microfabricated transistor and reduce the power consumption of the device, in order to achieve fast operation the MOS transistor is required to have a threshold voltage Vth reduced in absolute value as an operating power supply voltage is reduced.
A MOS transistor, however, conducts a current referred to as a sub threshold leakage current (referred to as an “off leak current” hereinafter) between its source and drain even when it is turned off. When a threshold voltage is reduced in absolute value, an increased off leak current flows. Since an absolute value of a threshold voltage has a negative temperature-dependency and thus reduces as temperature rises, an increased operating temperature causes an increased off leak current and hence an increased direct current in the entirety of a large scale integrated circuit. In particular, in a dynamic semiconductor memory device, a current flowing in a standby state (a standby current) is disadvantageously increased.
In order to reduce current consumption in the standby state without degrading high speed operability, there has been conventionally proposed a hierarchical power supply configuration or an MT-CMOS (Multi Threshold-CMOS) configuration, as disclosed, e.g., in Japanese Patent Laying-Open No. 6-237164 and Ultra LSI Memory, by Ito 1994, published by Baihukan.
FIG. 60
shows an example of a conventional MT-CMOS configuration. In
FIG. 60
, cascaded CMOS inverters IV
1
-IV
5
of five stages are shown as an internal circuit. An input signal IN fed to the first-stage inverter IV
1
is at a low level in a standby cycle. CMOS inverters IV
1
-IV
5
have an identical configuration and each includes a p channel MOS transistor PT and an n channel MOS transistor NT. MOS transistors PT and NT each are a low threshold voltage (L-Vth) MOS transistor with its threshold voltage reduced in absolute value.
For inverters IV
1
-IV
5
, there are provided a main power supply line
1
receiving a power supply voltage Vcc, a sub power supply line
3
coupled with main power supply line
1
via a leakage-cutting p channel MOS transistor PQ, a main ground line
2
transmitting a ground voltage Vss, and a sub ground line
4
connected to main ground line
2
via a leakage-cutting n channel MOS transistor NQ. Leakage-cutting MOS transistors PQ and NQ are an (M-Vth) MOS transistor which has a threshold voltage greater in absolute value than MOS transistors PT and NT have.
MOS transistor PQ has its gate receiving a control signal /&phgr; and MOS transistor NQ has its gate receiving a control signal &phgr;. Control signal &phgr; attains a high level in an active cycle in which the internal circuit operates, and control signal &phgr; attains a low level in a standby cycle in which the internal circuit is set in a standby state. Control signal /&phgr; attains a low level in the active cycle and a high level in the standby cycle.
In the internal circuit, odd-stage inverters IV
1
, IV
3
and IV
5
. . . have sources of their p channel MOS transistors PTs connected to main power supply line
1
and sources of n channel MOS transistors NTs connected to sub ground line
4
. Even-stage inverters IV
2
, IV
4
, . . . have sources of their p channel MOS transistors PTs connected to sub power supply line
3
and sources of their n channel MOS transistors NTs connected to main ground line
2
. An operation of the MT-CMOS configuration shown in
FIG. 60
will now be briefly described with reference to the signal waveform diagram shown in FIG.
61
.
In the standby cycle, control signal &phgr; is at a low level and control signal /&phgr; is at a high level, and input signal IN is at a low level. In this state, leakage cutting MOS transistors PQ and NQ are turned off. In odd-stage inverters IV
1
, IV
3
, and IV
5
, their p channel MOS transistors PTs are turned on and their n channel MOS transistors NTs are turned off, since input signal IN is at a low level. The p channel MOS transistors PTs have their sources connected to main power supply line
1
and the n channel MOS transistors NTs have their sources connected to sub ground line
4
. When p channel MOS transistor PT transmits to a corresponding output node (or drain) a voltage of the power supply voltage Vcc level on main power supply line
1
, its source and drain voltages are equalized and the transistor does not conduct.
The n channel MOS transistor NT receiving a low level signal at the gate, causes off leak current. Sub ground line
4
is connected to main ground line
2
via leakage cutting MOS transistor NQ having the relatively high threshold voltage M-Vth. Thus, when off leak currents from inverters IV
1
, IV
3
and IV
5
flow to sub ground line
4
, leakage cutting MOS transistor NQ cannot discharge all of the off leak currents and a voltage level SVss on sub ground line
4
becomes higher than ground voltage Vss. The level of voltage SVss on sub ground line
4
is ultimately determined by a relationship between the amount of the leakage current discharged by leakage cutting MOS transistor NQ and the sum of all of the off leak currents from the inverter stages included in the internal circuit. When voltage SVss on sub ground line
4
becomes higher than ground voltage Vss, in odd-stage inverters IV
1
, IV
3
, IV
5
their n channel MOS transistors NTs have their respective gates and respective sources reverse-biased, resulting in a further reduced off leak current.
In even-stage inverters IV
2
, IV
4
. . . , input signal IN is at a high level. Even-stage inverters IV
2
, IV
4
, . . . have their p channel MOS transistors PTs connected at the respective sources to sub power supply line
3
and their n channel MOS transistors NTs connected at the respective sources to main ground line
2
. Thus, in even-stage inverters IV
2
, IV
4
, . . . their n channel MOS transistors have their sources and drains both set at the ground voltage Vss level and thus do not conduct and cause no off leak current. The p channel MOS transistors PTs, however, cause off leak current. Between main power supply line
1
and sub power supply line
3
, leakage-cutting MOS transistor PQ is set to have a threshold voltage of a relatively large absolute value (M-Vth). Thus, the amount of the leakage current from main power supply line
1
to sub power supply line
3
is determined by leakage cutting MOS transistor PQ, and voltage SVcc on sub power supply line
3
becomes lower than the power supply voltage Vcc level. The voltage SVcc level on sub power supply line
3
is ultimately determined by a relationship between the leakage current from leakage cutting MOS transistor PQ and the sum of all of the off leak currents in even-stage inverters IV
2
, IV
4
, . When voltage SVcc is lower than power supply voltage Vcc, in even-stage inverters IV
2
, IV
4
. . . their p channel MOS transistors PTs have the respective gates and respective sources reverse-biased, resulting in a further reduced off leak current.
In the active cycle, control signal &phgr; attains a high level and control signal/&phgr; attains a low level, leakage cutting MOS transistors PQ and NQ are turned on, main power supply line
1
is connected to s

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