Semiconductor memory device with reduced consumption power and r

Details Semiconductor memory device with reduced consumption power and r Semiconductor memory device with reduced consumption power and r

1994-08-26

1996-10-08

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

365226, 365227, G11C 700

Patent

active

055638376

ABSTRACT:
A semiconductor memory device having a reduced consumption power at a periodic self-refreshing operation and a refreshing method of this semiconductor memory device, in which a supply voltage to an internal circuit is restricted in a self-refreshing operation period to reduce consumption power. A first internal reference voltage generated by an internal reference voltage generator is dropped in a voltage down circuit to obtain a second internal reference voltage. An internal operation voltage switching circuit switches the first and second internal reference voltages by a timing of a self-refreshing entry signal to output the selected one of these voltages to the internal circuit. The voltage down circuit includes two voltage dividing resistors and an amplifier, and the internal operation voltage switching circuit includes a first and second CMOS bus transistor devices, each composed of two CMOS bus transistors. A restriction voltage is determined within a operation allowable range of the internal circuit.

REFERENCES:
patent: 5323354 (1994-06-01), Matsumoto et al.
patent: 5337282 (1994-08-01), Koike
patent: 5367487 (1994-11-01), Yoshida

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