Semiconductor memory device with reduced chip area

Details Semiconductor memory device with reduced chip area Semiconductor memory device with reduced chip area

1996-11-21

1998-03-03

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

36523006, G11C 1300

Patent

active

057242917

ABSTRACT:
A semiconductor memory has memory cells arranged in a matrix to form a memory cell block. A word line is connected to each row of memory cells. The cell block has a pair of data lines, a row decoder circuit for activating one of the word lines and the pair of data lines, and a column decoder circuit for generating read and write select signals to selectively activate a desired column of memory cells and set that column to either a read or write mode. Each memory cell column has a pair of digit lines, a sense amplifier for amplifying differential data signals on the digit lines and read and write data transfer circuits for transferring differential read and write data signals to the digit lines in the read and write modes. The read data transfer circuit includes a pair of first MOS transistors connected to the data lines and activated with the read select signal, and a pair of second MOS transistors connected to the first MOS transistors in series. The gates of the second MOS transistors are connected to the digit lines. The second MOS transistors are operable to drive the data lines via the first MOS transistors by the differential read data signals in the read mode. The write data transfer circuit includes a pair of third MOS transistors provided between the data lines and the digit lines and activated with the write select signal.

REFERENCES:
patent: 4472792 (1984-09-01), Shimohigashi et al.
Komatsuzaki et al., "Circuit Techniques For a Wide Word I/O Path 64 Meg DRAM", Symposium on VLSI Circuits Digest of Technical Papers, pp. 133-134, 1991.

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