Semiconductor memory device with reduced...

Details Semiconductor memory device with reduced... Semiconductor memory device with reduced...

2000-04-27

2002-08-20

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S297000, C257S298000, C257S301000, C257S302000, C257S303000, C257S305000

Reexamination Certificate

active

06437381

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to vertical transistor structures in the trench capacitors of Dynamic Random Access Memory (DRAM) cells and, more specifically, to a process for manufacture of such structures.
BACKGROUND OF THE INVENTION
Semiconductor memory devices comprising vertical transistor structures in trench capacitors are well known in the art to save surface area on electronic circuits such as DRAM chips.
FIG. 1
schematically illustrates a typical semiconductor memory device. A more detailed depiction of such a semiconductor memory device is provided in FIG.
12
. Semiconductor memory device
10
comprises a capacitor trench
12
, an isolation or “trench top” oxide (TTO)
14
, a gate oxide
16
, diffusion regions (contact implants)
18
, a gate contact
220
, a source contact
222
, and gate sidewall isolation spacers
240
. Of the elements of semiconductor memory device
10
, only gate contact
220
, source contact
222
, and gate sidewall isolation spacers
240
are above the surface
21
of the substrate
24
, which is typically a silicon wafer.
FIG. 2
is a cross section taken along line
2
—
2
in FIG.
1
. As shown in
FIG. 2
, gate oxide
16
forms a continuous faceted wall formed of planes aligned with the (
100
) and (
110
) crystal planes for a silicon wafer with a (
100
) surface orientation. The silicon wafer may have any surface orientation, however, as is known in the art.
A crystal contains planes of atoms which influence the properties and behavior of a material. Thus, it is advantageous to identify various planes within crystals. In accordance with standard crystallographic nomenclature, such identification is done using Miller indices: three numbers within parentheses, namely (hkl). A plane that intersects the x, y, and z axes at 1, 1, and 0.5, respectively, is represented as (
112
). The Miller indices are the reciprocals of the three axial intercepts for a plane, cleared of fractions and common multipliers.
Further in accordance with standard crystallographic nomenclature, various symbols have specified meanings. Among those symbols are rounded brackets, { }, which refer to families of equivalent crystallographic planes (e.g., the {001} family of planes); parentheses, ( ), which refer to specific crystallographic planes (e.g., the (100) plane); horizontal triangles, ⋄, which refer to families of equivalent crystallographic axes (e.g., the <011> family of axes); and square brackets, [ ], which refer to a specific crystal axis (e.g., the [110] axis). For example, in silicon crystals, the (100) plane and the (001) plane are equivalent to one another and, thus, are both in the same {001} family of planes.
The oxidation step used to form gate oxide
16
is strongly crystal orientation dependent. That is, the thickness of the oxide formed after a given time at a given temperature is dependent on the crystal orientation of the underlying silicon. Thus, the gate oxidation step tends to form gate oxide
16
with a thickness d
1
in the (110) planes that is greater than thickness d
2
in the (100) planes. The non-homogenous gate oxide thickness leads to weak points at the thinner sections where the time to breakdown is reduced relative to the rest of the gate oxide.
Similarly, the crystal dependency during oxidation steps also affects the creation of other oxides in DRAM trench structures, such as the “LOCOS collar,” described below. Referring now to
FIGS. 3-12
, in which like reference numbers refer to like elements throughout, there is shown various aspects of an exemplary DRAM cell and intermediate steps in an exemplary process for making the cell. These process steps are disclosed by U.S. patent application Ser. No. 09/359,292 filed on behalf of Gary Bronner et al., assigned to the common assignee of this invention, and incorporated herein by reference.
As shown in
FIG. 3
, a typical deep trench storage capacitor of semiconductor memory device
10
is formed into a pad
22
and a substrate
24
by conventional processing techniques well known in the art. For example, an optical lithography step may be used to form a pattern on pad
22
. Then a dry etching step, such reactive-ion etching (RIE), may be used to create a trench
20
to a desired depth through pad
22
and into substrate
24
.
Deep trench
20
generally has a depth of about 3 &mgr;m to about 10 &mgr;m and a diameter or maximum width that is a function of the lithographic ground rule, typically about 0.5 &mgr;m to less than 0.1 &mgr;m. Trench
20
has sidewalls
32
and a bottom
33
.
As shown in
FIG. 4
, an isolation collar
26
is formed in an upper region
28
of trench
20
. Upper region
28
typically comprises 10-20% of the total depth of trench
20
. Collar
26
may be formed using a local thermal oxidation (LOCOS) process, such as by the exemplary process explained below, or by other physical and chemical mechanisms, as also indicated below. Because of the traditional use of the LOCOS process, isolation collar
26
is sometimes referred to as a LOCOS collar.
Before the oxidation step, a barrier film (not shown) may be formed along the exposed surfaces of trench
20
and pad
22
such as by a low-pressure chemical vapor deposition (LPCVD) of a SiN film having a thickness of about 2 nm to about 10 nm. The barrier film is then removed from upper region
28
, for example by filling trench
20
with photoresist (not shown) and partially etching the photoresist down into trench
20
to a depth controlled by the amount of overetch time. This step exposes the barrier film in upper region
28
while leaving the lower region
30
covered. The exposed barrier film may then be removed in upper region
28
of trench
20
and from pad layer
22
, for example, by chemical or dry etching, and then the photoresist stripped away. Other processes for isolating sidewall
32
in upper region
28
while protecting sidewall
32
in lower region
30
may also be used.
The local oxidation step is then performed. The oxidation step may be conducted, for example, at oxidation conditions that promote the oxidation rate along one family of crystal axes over another. Such oxidation conditions induce faceting of the underlying silicon substrate
24
during growth of collar
26
. Such a faceted collar may have a cross section similar to that shown for gate oxide
16
as illustrated in
FIG. 2
, where thickness di of the oxide aligned with one plane is greater than thickness d
2
of the oxide aligned with another crystal plane. Because of the different oxidation rates of the different crystal orientations, in order to achieve a minimum collar thickness on all of the sidewalls, regardless of crystal orientation, an unnecessary, increased thickness may be required on the sidewall having the faster-growing orientation. The thermal oxide collar
26
and associated faceting are formed only on sidewalls
32
in upper region
28
of trench
20
; the barrier film protects sidewalls
32
in lower region
30
of trench
20
.
Next, the barrier film in lower region
30
is typically stripped via a process that selectively leaves thermal oxide isolation collar
26
in upper region
28
of trench
20
. A buried plate
34
is then created in lower region
30
, leaving the configuration shown in FIG.
4
. Buried plate
34
may be created by doping lower region
30
of trench
20
to form an out-diffusion in substrate
24
using collar
26
as a mask for upper region
28
. The out-diffusion may be formed using arsenosilicate glass (ASG) drive-in, plasma doping (PLAD), plasma ion implantation (PIII), gas-phase diffusion of arsenic (As) or phosphorus (P), or other techniques known in the art.
Next, as shown in
FIG. 5
, a thin node dielectric
35
is created, such as by thermal nitridation, for example with ammonia (NH
3
), followed by LPCVD of SiN. Finally, trench
20
is filled, such as with an n+ doped LPCVD polysilicon
36
, and recessed to a desired depth D
1
. Depth D
1
is typically about 300 nm to about 700 nm, preferably between 300

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