Semiconductor memory device with reduce coupling capacitance

Details Semiconductor memory device with reduce coupling capacitance Semiconductor memory device with reduce coupling capacitance

2001-01-16

2002-11-26

Ho, Hoai (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S368000

Reexamination Certificate

active

06486519

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly relates to a semiconductor memory device provided with a bit line configuration by which a coupling capacitance between mutually adjacent bit lines can be reduced.
2. Description of the Related Art
FIG. 5
is a circuit diagram showing one part of a conventional ROM (Read Only Memory). In the figure, reference numerals
101
(i=1 to 6) denote memory cells. Note that although the memory cells
101
i
are aligned in two lines and three columns in this figure, a plurality of memory cells
101
i
are aligned in a matrix form in the longitudinal and lateral directions in accordance with the total memory capacity of the memory device itself in reality. Reference numerals
102
i
(i=1 to 6) denote transistors each configuring the corresponding memory cell, numerals
103
i
(i=1, 2) denote word lines which are connected to the gate of each of the transistors
102
i
extending in the lateral direction, and numerals
104
i
(i=1 to 3) denote bit lines which are extending along the transistors
102
i aligned in the longitudinal direction and can be connected to the drain of each of the transistors
102
i
. Further, numeral
105
denotes an output line for reading data stored in the target memory cell,
106
denotes a selector for selecting the bit lines
104
i
connected to the output line
105
,
107
denotes a signal line for transmitting a control signal for controlling the selector
106
,
108
denotes a voltage source,
109
denotes a signal line for transmitting a signal for controlling the precharging operation,
110
denotes a transistor, which is switched on and off in accordance with the control signal transmitted by way of the signal line
109
and provides electric current when precharging the output line
105
and the bit line
104
i
selected by the selector
106
, and
111
denotes a sense amplifier for converting the voltage to be fed to the output line
105
to that of the logic level in accordance with the data stored in the target memory cell.
Note that the source of each of the transistors
102
i
is grounded, and that storing data in the ROM shown in
FIG. 5
is carried out by connecting and/or disconnecting the drain of each of the transistors
102
, configuring the corresponding memory cell
101
i
, depending on whether the data to be stored is “0” or “1”. In the ROM shown in
FIG. 5
, by connecting the drain of each of the transistors
102
1
,
102
3
,
102
4
,
102
5
and
102
6
to the respectively corresponding bit lines
104
i
, the binary data “0” (low potential VL) is stored, whereas by disconnecting, or releasing the drain of the transistor
102
2
from the corresponding bit line
104
2
, the binary data “1” (high potential VH) is stored. The connection of the drain of each of the transistors with the corresponding bit line can be implemented by providing a through-hole between the drain and the corresponding bit line. Thus, forming or not forming the through-hole to each of the memory cells can be determined depending on what kind of data or program is to be stored in the ROM.
The operation of the conventional memory device is now explained below.
When reading a data, first a signal of “H” level is input to the signal line
109
to set ON the transistor
110
, so as to precharge the output line
105
with a voltage in the region greater than the low potential VL but less than the high potential VH. Then, an appropriate signal is input to the signal line
107
thereby to connect the bit line
104
i
related to a read target memory cell (here, the target memory cells are considered to be of limited numbers just for convenience) with the output line
105
by way of the selector
106
, so as to precharge also the bit line
104
i
with a voltage in the region greater than the low potential VL but less than the high potential VH, in addition to the output line
105
i
. After the selected bit line
104
i
is precharged, the voltage of the corresponding word line
103
i
related to the read target memory cell is set to the “H” level, and the transistor
102
i
whose gate is connected to the thus selected word line
103
is set to ON. Concerning the read target memory cell, in the case where the drain of the ON-set transistor
102
i
is connected to the corresponding bit line
104
i
(namely the case of either one of the transistors
102
1
,
102
3
,
102
4
,
102
5
and
102
6
), the precharged potential flows into the ground to thereby lower the potential of the corresponding bit line
104
i
. Further, in the case where the drain of the ON-set transistor
102
, is not connected to the corresponding bit line
104
i
(namely the case of the transistors
102
2
), the potential of the corresponding bit line
104
i
is not changed, and these changes of the potential are detected by the sense amplifier
111
, and the voltage of the logic level corresponding to the data is output, depending on whether the binary data stored in each of the memory cells is “1” or “0”.
FIG. 6
is a plain view showing the layout regarding one part of the configuration of a conventional ROM. The layout shown in
FIG. 6
corresponds to the portion enclosed by the dotted lines shown in FIG.
5
. Further,
FIG. 7
is a schematic sectional view regarding the portion observed from the line cut along A—A of
FIG. 6
, whereas
FIG. 8
is a schematic sectional view regarding the portion observed from the line cut along B—B of FIG.
6
. In these figures, reference numerals
112
1
and
112
2
denote gate sections made of Polysilicon (hereinafter referred to just as “poly”), each of which is common to the set of transistors
102
1
,
102
2
and
102
3
, and to the set of
102
4
,
102
5
and
102
6
, which are connected respectively to the word lines
103
1
and
103
2
. Numeral
113
denotes a contact for connecting a first aluminum (1AL) and the poly or a substrate,
114
denotes a first through-hole for connecting the first aluminum (1AL) and a second aluminum (2AL), and
115
denotes a second through-hole for connecting the second aluminum (2AL) and a third aluminum (3AL). It should be noted that in the plain view of the layout shown in
FIG. 6
, an overlap of the contact
113
, the first through-hole
114
and the second through-hole
115
is represented by the overlap of symbols indicating each of these members. For example, by the symbol denoted by a reference character X, it can be deduced that the contact
113
denoted by a longitudinal line, the first through-hole
114
denoted by a lateral line and the second through-hole
115
denoted by a rightwardly ascending slant line are aligned in the vertical direction. Further, numeral
116
denotes a drain, and
117
denotes a source, wherein one source is shared by every two word lines (for example, the word line
103
1
and the word line
103
2
) concerning the transistors configuring the memory cells connected to these two corresponding word lines. Further, numeral
118
denotes a grounding line, and by connecting the source
117
to this ground lead
118
, the source
117
can be grounded. Further, in
FIG. 6
, the portion enclosed by the dotted lines is a diffusion region, showing the area in which each of the transistors is formed.
Since the drain of the transistor
102
2
configuring a memory cell is not formed with the second through-hole as indicated by the symbol of the corresponding portion, the drain of the transistor
102
2
is not connected to the bit line
104
2
, but is made an open output. Further, the drain of each of the transistors
102
1
,
102
3
,
102
4
,
102
5
and
102
6
is, as shown by the symbol of the corresponding portion, formed with the second through-hole, so that the drain of each transistor is connected to the third aluminum (3AL), namely to the bit line
104
1
.
Since the conventional semiconductor memory device is configured as mentioned above, all the bit lines are configured by the metal lines in the same layer, and in accordance with a progre

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