Semiconductor memory device with readout data buses connecting l

Details Semiconductor memory device with readout data buses connecting l Semiconductor memory device with readout data buses connecting l

1991-02-12

1993-08-24

Mottola, Steven

Static information storage and retrieval

Read/write circuit

Including signal clamping

365207, G11C 700

Patent

active

052395073

ABSTRACT:
Readout data amplified by each local sense amplifier is provided to the corresponding readout data bus. Each readout data bus is connected to a plurality of main sense amplifiers (for example, a main sense amplifier for x1 and a main sense amplifier for x2). Each main sense amplifier includes a clamp transistor for clamping the potential of the readout data bus always to a constant potential, whereby increase in speed of readout data is performed by the clamp transistor. The base potential of the clamp transistor in each main sense amplifier is controlled in response to a switching control signal. As a result, a plurality of main sense amplifiers connected to one readout data bus are switched selectively.

REFERENCES:
patent: 4866674 (1989-09-01), Tran
patent: 4907203 (1990-03-01), Wada et al.
patent: 5093806 (1992-03-01), Tran

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