Semiconductor memory device with provision of pseudo-acceleratio

Details Semiconductor memory device with provision of pseudo-acceleratio Semiconductor memory device with provision of pseudo-acceleratio

1994-01-13

1994-11-15

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

365193, 365194, G11C 2900

Patent

active

053654820

ABSTRACT:
In a semiconductor memory device including memory cells connected to word lines, one of the word lines is selected by a word line selecting circuit. A word line driving circuit receives an activation signal and a pseudo-acceleration signal to generate a driving signal for driving the selecting circuit. The driving signal is generated by delaying the activation signal with a definite delay time period which is changed in response to the pseudo-acceleration test signal, to thus perform a pseudo-acceleration test upon the word line driving circuit.

REFERENCES:
patent: 5060198 (1991-10-01), Kowalski
patent: 5184327 (1993-02-01), Matsuda et al.
patent: 5204837 (1993-04-01), Suwa et al.
patent: 5208778 (1993-05-01), Kumanoya et al.
patent: 5251180 (1993-10-01), Ohshima
G. J. Rudy, "Memory Word Line Monitor", IBM Technical Disclosure Bulletin, vol. 19, No. 2, Jul. 1976, p. 499.

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