Semiconductor memory device with predecoder

Details Semiconductor memory device with predecoder Semiconductor memory device with predecoder

1998-10-23

2000-05-16

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, 36523001, G11C 700

Patent

active

060646071

ABSTRACT:
Each of first and second program circuits includes a determination node, first to fourth fuses, first to fourth N channel MOS transistors, and first to fourth supply lines. The first to fourth N channel MOS transistors receive first to fourth row address predecode signals, respectively. The first N channel MOS transistor included in the first program circuit and the first N channel MOS transistor included in the second program circuit are arranged adjacent to each other. The first supply line provides a first row address predecode signal to the gate of these two N channel MOS transistors. The same applies for the second to fourth N channel MOS transistors and the second to fourth supply lines. Accordingly, the interconnection capacitance of the row address predecode signal line can be reduced. Also, the size of the transistor driving the row address predecode signal and the transistors in the program circuit can be reduced to allow a smaller layout area for the entire chip.

REFERENCES:
patent: 5469391 (1995-11-01), Haraguchi
patent: 5519657 (1996-05-01), Arimoto
patent: 5689465 (1997-11-01), Sukegawa et al.
patent: 5835424 (1998-11-01), Kikukawa et al.

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