Semiconductor memory device with P-channel MOS transistor load c

Details Semiconductor memory device with P-channel MOS transistor load c Semiconductor memory device with P-channel MOS transistor load c

1984-05-16

1990-04-10

Gossage, Glenn A.

Static information storage and retrieval

Floating gate

Particular biasing

36518909, 365181, 365208, 365210, 307530, G11C 1140

Patent

active

049166654

ABSTRACT:
A semiconductor memory device of the invention has a plurality of floating gate memory cells. A detector detects the data stored in a floating gate memory cell selected by a decoder and produces a corresponding detection signal. A load circuit amplifies the detection signal. The amplified detection signal is supplied to a differential amplifier. The differential amplifier compares the voltage of the amplified detection signal with a reference voltage from a reference voltage generator and produces a binary signal corresponding to the storage contents in the floating gate memory. The load circuit is a p-channel enhancement-type MOS transistor. The load transistor has a gate and drain which are connected to the node between the detector and the differential amplifier, and also has a source and substrate which receive a predetermined voltage.

REFERENCES:
patent: 4103345 (1978-07-01), Suzuki et al.
patent: 4217535 (1980-08-01), Suzuki et al.
patent: 4223394 (1980-09-01), Pathak et al.
patent: 4504748 (1985-03-01), Oritani
Richman, "Characteristics and Operation of MOS Field Effect Devices", 1967, pp. 121-126.
M. Isobe et al., "An 18 ns CMOS/SOS 4K Static RAM", IEEE Journal of Solid-State Circuits, vol. SC-16, no. 5 (Oct. 1981), pp. 460-464.
Tietze, Schenk, "Korrigierter Nachdruck der dritten Auflage", Halbleiter-Schaltungstechnik, pp. 503-506 (1976).

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