Semiconductor memory device with on die termination circuit

Details Semiconductor memory device with on die termination circuit Semiconductor memory device with on die termination circuit

2006-12-29

2009-02-24

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S028000

Reexamination Certificate

active

07495468

ABSTRACT:
A semiconductor memory device includes: a termination resistance supply unit connected to a pad to supply termination resistances corresponding to a plurality of control signals; a decoding unit for decoding the plurality of ODT setting signals to output an ODT enable signal and a plurality of decoding output signals; a control signal generating unit for receiving the plurality of decoding output signals to output the plurality of control signals in response to an ODT off signal and a clock signal; and an output control unit for activating one of the plurality of control signals when a read enable detection signal is activated.

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patent: 7312627 (2007-12-01), An
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patent: 10-2006-0038234 (2006-05-01), None
patent: 10-2006-0038745 (2006-05-01), None

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