Semiconductor memory device with on-chip boosted power supply vo

Details Semiconductor memory device with on-chip boosted power supply vo Semiconductor memory device with on-chip boosted power supply vo

1996-11-22

1998-05-26

Nelms, David C.

Static information storage and retrieval

Powering

36518909, 36518911, 327589, 257372, G11C 700

Patent

active

057577145

ABSTRACT:
A semiconductor memory device uses three different power supply voltage levels including an internal IVcc, ground Vss and a boosted level Vpp more positive than the internal Vcc. A precharge control circuit in the memory device includes at least one NMOS transistor, at least one PMOS transistor and an output node having voltage values ranging from the IVcc either to Vss or to Vpp. The NMOS transistor acts as a loading transistor to the PMOS transistor and prevents latch-up in the PMOS transistor by maintaining IVcc below Vpp during the initial power set-up period of the memory device.

REFERENCES:
patent: 5315188 (1994-05-01), Lee
patent: 5406523 (1995-04-01), Foss et al.
patent: 5530640 (1996-06-01), Hara et al.
patent: 5563842 (1996-10-01), Challa

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