Semiconductor memory device with noise reduction system

Details Semiconductor memory device with noise reduction system Semiconductor memory device with noise reduction system

1991-05-24

1994-01-18

Mullins, James B.

Static information storage and retrieval

Read/write circuit

Noise suppression

G11C 702

Patent

active

052804534

ABSTRACT:
An integrated circuit semiconductor memory device includes a memory array having memory cells. A sensing circuit is coupled to the memory cells through one of first and second bit lines. A first conductive line is for applying a first voltage potential to the sensing circuit, and a second conductive line is for applying a second voltage potential to the sensing circuit. A first field effect transistor is provided having first, second electrodes connected to the first conductive line, and a gate electrode connected to the second conductive line. The sensing circuit has a second field effect transistor and a third field effect transistor of an opposite channel type to the second field effect transistor. The first, second and gate electrodes of the first field effect transistor are formed substantially simultaneously with the first, second and gate electrodes of one of the second and third field effect transistors during manufacture of the integrated circuit semiconductor memory device. Also, the first conductive line is formed substantially simultaneously with the second conductive line during manufacture of the integrated circuit semiconductor memory device.

REFERENCES:
patent: 5030859 (1991-07-01), Ihara

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