Semiconductor memory device with multiplied internal clock

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

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713400, 711100, G06F 1342, G06F 1200, H04L 700

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active

060473444

ABSTRACT:
The practical operation speed of the memory device is increased by multiplexing input and output signals so as to increase the internal operation frequency higher than the external clock frequency. The feature of the memory device of the present invention is that it has the function of making the internal operation frequency higher than the external clock frequency by making the external bit width larger than the internal bit width, writing write data by dividing them successively by time division operation, into those having an internal bit width, and allocating read data to use an entire external bit width. According to the present invention, the practical operation speed of the memory device assembled on the board can be increased over the upper frequency limit of signals transmitted through the wiring on the board, and the high frequency performance of the memory device can be tested at the step of the die sorting test.

REFERENCES:
patent: 5457696 (1995-10-01), Mori
patent: 5499384 (1996-03-01), Lentz et al.
patent: 5598554 (1997-01-01), Litaize et al.

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