Semiconductor memory device with multiple sub-arrays of...

Details Semiconductor memory device with multiple sub-arrays of... Semiconductor memory device with multiple sub-arrays of...

1999-11-30

2001-04-03

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S231000, C365S230010, C365S230060

Reexamination Certificate

active

06212121

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device with sub-arrays of different sizes.
BACKGROUND OF THE INVENTION
In a semiconductor memory device such as a dynamic random access memory (referred to as “DRAM”), a memory cell array typically contains multiple sub-arrays
10
such as illustrated in FIG.
1
. Each of the sub-arrays
10
contains multiple word lines WLi (for i equal to 1 to m), multiple bit lines BLj (for j equal to 1 to n), and multiple memory cells MC at intersections of the word lines WLi and the bit lines BLj. Each of the memory cells MC includes a switching transistor (charge transfer transistor) and a capacitor. The gates of the switching transistors couple to corresponding word lines WL
1
to WLm, and current paths through the switching transistors are between corresponding bit lines BL
1
to BLn and a voltage VP through the corresponding capacitors. Bit lines BL
1
to BLn of the respective sub-arrays
10
come in pairs. For example, two adjacent bit lines BLj and BL(j+1) constitute a pair. Multiple sense amplifiers
12
, each coupled to pairs of bit lines, are between the sub-arrays
10
and shared by two adjacent sub-arrays
10
.
As well known in the art, bit line loading and word line loading increases with the number of memory cells coupled to a word line and a bit line, respectively. Increasing the bit line loading generally increases bit line capacitance and requires improvements in the sensing capability of an attached sense amplifier. Otherwise, the sense amplifier may have difficulty when attempting to sense and amplify a voltage difference between bit lines within a required sensing time. Generally, the sensing capability must match the bit line loading. Accordingly, the sensing ability of the sense amplifiers limits the maximum number of memory cells that can be coupled to a bit line.
Generally, to simplify addressing of the word lines, the number of memory cells on each bit line of each sub-array
10
is a power M of 2 (2
M
). If the loading per memory cell on the respective bit line is halved, two sub-arrays can be combined into a sub-array having bit lines that are twice as long, and the sense amplifiers can still service the larger sub-array. To achieve the same total memory capacity, a memory with the larger sub-arrays requires fewer sub-arrays and fewer sense amplifier regions between the sub-arrays. Similarly, a two-fold improvement in the sense capability of the sense amplifiers allows doubling of the bit line loading, decreasing the number of sub-arrays
10
by half, and reducing the number of sense amplifiers
12
required for a fixed total memory capacity. However, if the sensing capability of the sense amplifiers or the bit line loading is not improved by at least a factor of two, the number of sense amplifier regions cannot be reduced because conventional addressing requires the subarrays to contain 2
M
memory cells per bit line. The number of memory cells per bit line cannot be doubled unless sensing capability improves by at least a factor of two. Accordingly, when the sensing capability of the sense amplifiers improves by 1.5 times or the bit line capacitance decreases by 25%, the number of the sub-arrays must be maintained despite the improvement. This means the loss of chip efficiency.
SUMMARY OF THE INVENTION
In accordance with an aspect of the present invention, a semiconductor memory device has sub-arrays where the number of word lines in the sub-array is not a power of two. Accordingly, a reduction in the amount of sensing circuitry can be achieved when the sensing capability of sense amplifiers improves by less than a factor of two.
In one embodiment of the present invention, a semiconductor memory device includes a memory cell array that is divided into a plurality of sub-arrays. Each of the sub-arrays contains a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at intersections of the word lines and the bit lines. Among the sub-arrays, the number of memory cells coupled to the respective bit lines of in at least one sub-array differs from the number of memory cells coupled to the respective bit lines in other sub-arrays.
In accordance with another embodiment, a semiconductor memory device includes a plurality of the sub-arrays and a sub-array selection circuit. Each sub-array comprises a plurality of word lines, a plurality of bit lines and a plurality of memory cells arranged at intersections of the word lines and the bit lines. In at lease one of the sub-arrays, the number of addressable word lines is not a power of two. Accordingly, a row address for the memory does not partition neatly into bits designating a sub-array and bits designating a word line in the sub-array. The selection circuit generates a plurality of selection signals designating which of the sub-arrays are accessed. In response to an address signal corresponding to a word line in the first sub-array, the selection circuit asserts a first of the selection signals to designate access of the first sub-array. In one embodiment, the selection circuit includes a predecoder and a decoder. The predecoder generates one or more set of decoded signals from a received address signal. One set of the decoded signals corresponds to a memory section including 2
M
word lines for some integer M, and is asserted to indicate the access of a memory cell in the corresponding memory section. One or more address bit or a second set of decoded signals indicates a relative position of the accessed word line within a memory section. The decoder couples to the predecoder and generates the selection signals using the decoded signals alone or with one or more signals indicating bits of the address.


REFERENCES:
patent: 6041016 (2000-03-01), Freker
patent: 6046923 (2000-04-01), Evans
patent: 6094382 (2000-07-01), Choi et al.
patent: 6098145 (2000-08-01), Huang

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