Semiconductor memory device with multiple alternating decoders c

Details Semiconductor memory device with multiple alternating decoders c Semiconductor memory device with multiple alternating decoders c

1988-06-17

1989-09-12

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

36523005, 36523006, 36518904, G11C 700, G11C 800

Patent

active

048666777

ABSTRACT:
A semiconductor memory device includes a first row decoder and memory cells M11 to MNL. The first row decoder receives the row address signal from an input buffer and a specific row fo a matrix array of memory cells M11 to MNL. The memory device further includes a second row decoder, a refresh address generator, a timing controller and switching circuits. The second row decoder selects a specific row of the matrix array according to a refresh address derived from the refresh address generator. The output terminals of the first and second row decoders, are connected to the memory cells through groups of switching circuits. The timing controller selectively renders conductive either the switching circuit group.

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