Semiconductor memory device with multibank structure

Details Semiconductor memory device with multibank structure Semiconductor memory device with multibank structure

1996-09-17

1998-08-25

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523001, 36523008, 365233, 36523003, G11C 800

Patent

active

057989788

ABSTRACT:
There is disclosed a semiconductor memory device that has a memory-cell array with memory cells arranged in a matrix, bit-line sense amplifiers connected to bit lines of the memory-cell array, a row address predecoder performing decoding of some of row address signals in response to a system clock, and a plurality of banks having an output line of the row address predecoder in common, includes: a row strobe buffer connected to an external system and producing a first control signal for selecting corresponding banks in response to the system clock, a row address strobe signal, and a bank selection address signal and for controlling generation of a row address sampling control signal; a row address sampling control signal generating circuit producing the row address sampling control signal in a predetermined period of time in response to generation of the first control signal produced by the row strobe buffer in order to control word-line activating and precharging operations; and a row decoder latching an output signal obtained by predecoding a row address with the output signal of the row address sampling control signal generating circuit.

REFERENCES:
patent: 5420869 (1995-05-01), Hatakeyama
patent: 5426606 (1995-06-01), Takai

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