Semiconductor memory device with miniaturization improvement

Details Semiconductor memory device with miniaturization improvement Semiconductor memory device with miniaturization improvement

2002-07-22

2003-09-16

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S368000, C257S401000

Reexamination Certificate

active

06621127

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same. More particularly, the invention relates to a technique for improving the stability of operation in an SRAM (Static Random Access Memory).
2. Description of the Background Art
In recent years, the level of integration and functionality of semiconductor devices have been remarkably on the increase, and there has been a demand for size reduction of semiconductor device structures. In the development of semiconductor devices, the size reduction of the semiconductor device structures greatly contributes to the reduction in chip area. Therefore, techniques for the size reduction of the semiconductor device structures are important. This is also true for SRAMs included in semiconductor memory devices without exception, and there has been an expectation for reduction in SRAM memory cell size.
An SRAM cell has transistors (driver transistors) constituting a flip-flop circuit for storing data therein, and transistors (access transistors) for switching.
FIGS. 19
,
20
,
21
A and
21
B illustrate background art steps of manufacturing an SRAM memory cell portion of a semiconductor memory device.
FIGS. 19
,
20
and
21
A are top views of the memory cell portion, and
FIG. 21B
is a sectional view taken along the line A-B of FIG.
21
A. The background art manufacturing steps of the SRAM memory cell portion will be described with reference to
FIGS. 19
,
20
,
21
A and
21
B.
Referring first to
FIG. 19
, an isolating insulation film
101
and a P type active region
102
defined by the isolating insulation film
101
are formed on a semiconductor substrate. An oxide film and an electrode material are deposited on the substrate and are selectively etched to form an access transistor gate electrode
103
and driver transistor gate electrodes
104
a
and
104
b
, as shown in FIG.
20
. Specifically, access transistors are to be formed in regions
105
a
and
105
b
shown in
FIG. 20
, and driver transistors are to be formed in regions
106
a
and
106
b
, respectively. An N type dopant is implanted by using the gate electrodes
103
,
104
a
,
104
b
as a mask to form N
−
source/drain regions
107
in the active region
102
except under the gate electrodes.
Next, a resist pattern having an opening corresponding to a region
108
shown in
FIG. 21A
is formed on the substrate, and an N type dopant is implanted by using the resist pattern as a mask. As a result, N
+
source/drain regions
109
are formed in the active region
102
within the region
108
. This forms the access and driver transistors constituting an SRAM cell. In
FIG. 21B
, the reference numeral
110
designates the semiconductor substrate.
Ensuring the stability of a stored data holding operation and a read operation of an SRAM requires a somewhat high conductance ratio between the driver transistors and the access transistors, that is, the resistance of the access transistors to be held somewhat high. For this purpose, the background art SRAM cell structure as shown in
FIG. 21A
is adapted such that the N
−
regions (or N
−
source/drain regions
107
) are formed, as shown, between the access transistor gate electrode
103
and the N
+
source/drain regions
109
to which a storage node is to be connected and are used as a resistance to ensure the somewhat high conductance ratio. However, advances in size reduction of semiconductor device structures have made it difficult to secure an area for the N
−
regions. Thus, an insufficient resistance formed using the N
−
regions leads to the degradation of the conductance ratio between the driver transistors and the access transistors.
A possible solution to such a problem is, for example, to reduce the width of the N
−
regions between the N
+
source/drain regions
109
and the access transistor gate electrode
103
by fine patterning during the formation of the active region
102
to increase the resistance of the N
−
regions. In this case, however, there is a danger that the gate width of the access transistors is varied due to misalignment of a mask pattern for the formation of the gate electrodes, which might result in the degradation of the stability of operation quality. In particular, it is very difficult to completely prevent such mask misalignment in the recent manufacture of semiconductor devices advanced in size reduction.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device which can ensure a good conductance ratio between driver and access transistors of an SRAM, require easy manufacturing steps and suppress the influence of mask misalignment, and a method of manufacturing the same.
According to the present invention, the semiconductor memory device includes a plurality of SRAM cells each having a driver transistor constituting a flip-flop circuit and an access transistor for switching. The gate electrode of the driver transistor, the gate electrode of the access transistor, and at least one dummy gate electrode are formed to cover part of an active region wherein source/drain diffusion layers of the access transistor and the driver transistor are formed. The source/drain diffusion layers are formed in only other than the part of the active region covered with the at least one dummy gate electrode.
A change may be made in position and shape of the dummy gate electrode to suppress the current driving capabilities of the access transistor and the driver transistor, thereby controlling a conductance ratio therebetween. Suppressing the current driving capability of the access transistor to suppress the conductance thereof increases the conductance ratio between the driver and access transistors to improve the stability of a stored data holding operation and a reading operation of the SRAM.
The dummy gate electrode may be formed in the same step as the gate electrodes of the driver and access transistors. Thus, there is no increase in the number of manufacturing steps, as compared with the background art method of manufacturing a semiconductor memory device. Additionally, there is no size reduction of a resist pattern for defining the active region and the source/drain diffusion layers. This holds the influence of mask misalignment as large as that of the background art semiconductor memory device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5396100 (1995-03-01), Yamasaki et al.
patent: 5889335 (1999-03-01), Kuroi et al.
patent: 6153476 (2000-11-01), Inaba et al.
patent: 6166425 (2000-12-01), Sakao
patent: 405206245 (1993-08-01), None

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