Semiconductor memory device with memory cell having low cell...

Details Semiconductor memory device with memory cell having low cell... Semiconductor memory device with memory cell having low cell...

2005-02-22

2005-02-22

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S190000, C365S203000

Reexamination Certificate

active

06859386

ABSTRACT:
In a memory cell, the cell ratio between an N-channel MOS transistor as a driver transistor and an N-channel MOS transistor as an access transistor is 1. To the first and second storage nodes, capacitors are connected, respectively. A word line driver receives a voltage obtained by boosting a power source voltage from a boosted power source voltage generating circuit and activates a word line with the boosted voltage. A bit line precharge circuit precharges bit lines to the power source potential when the word line is inactivated in accordance with a signal outputted from a BLPC signal generating circuit.

REFERENCES:
patent: 6141240 (2000-10-01), Madan et al.
patent: 6160733 (2000-12-01), Ebel
patent: 6650580 (2003-11-01), Braceras
patent: 62-257698 (1987-11-01), None
patent: 63-128662 (1988-06-01), None

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