Semiconductor memory device with less data transfer delay time

Details Semiconductor memory device with less data transfer delay time Semiconductor memory device with less data transfer delay time

2002-08-28

2004-02-03

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S233100, C711S167000, C711S005000

Reexamination Certificate

active

06687181

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory. More particularly, the present invention relates to a semiconductor memory in which data transfer from or to the external unit is carried out using the rising edge and falling edge of a clock signal.
2. Description of the Related Art
A semiconductor memory is conventionally known in which fast data transfer from or to the external is carried out using the rising edge and falling edge of a clock signal as triggers. Such a conventional semiconductor memory is disclosed in Japanese Laid Open Patent Application (JP-P2000-298983A).
As shown in
FIG. 1
, the conventional semiconductor memory is comprised of an input/output pad PA, a demultiplexer DE-MUX, serial-parallel converting circuits S-Pe and S-Po, write amplifiers WAe and WAo, memory cell arrays SAe and SAo, data amplifiers DAe and DAo, parallel-serial converting circuits P-Se and P-So, and a multiplexer MUX.
The demultiplexer DE-MUX divides inputted serial data containing 1-bit data into even data in the rising up of a basic clock signal CLK and odd data in the falling down of the basic clock signal CLK. The even data and the odd data are transferred to the memory cell arrays SAe and SAo by the buses
501
and
502
and are written therein, respectively. The memory cell array SAe is arranged nearer the input/output pad PA than the memory cell array SAo.
In case of a read operation, the even data and the odd data stored in the memory cell arrays SAe and SAo are transferred to the multiplexer MUX through the buses
503
and
504
, respectively. The multiplexer MUX outputs the even data and the odd data to the input/output pad PA in response to the rising edge and falling edge of the basic clock signal, respectively.
The even data contains bit data read first when the read operation is carried out. In the conventional semiconductor memory, the memory cell array SAe for storing the even data is arranged nearer the input/output pad PA than the memory cell array SAo. Thus, the length of the bus
503
for transferring the bit data read first when the read operation is carried out can be made short, resulting in realization of a high-speed operation.
However, in recent years, the high integration of the semiconductor memory elongates the distance between the memory cell array and the input/output pad. In accompaniment to this, the length of the bus for transferring data between the memory cell array and the input/output pad increases. The increase of the length of the bus causes the increase of a delay time in the data transfer. The conventional semiconductor memory is effective to shortening the time from the issuance of a read instruction to the output of data. However, the conventional semiconductor memory cannot solve the problem of the increase of the delay time due to the increase of the length of buses fundamentally.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a semiconductor memory device in which a delay time due to increase of the length of a bus can be made small in data transfer between a memory cell and an input/output pad.
Another object of the present invention is to provide a semiconductor memory device in which the number of buffers relating to the data transfer can be reduced.
In an aspect of the present invention, a semiconductor memory device includes a memory cell array which has an even bank activated based on even numbered addresses and an odd bank activated based on odd numbered addresses, a first even data bus connected with the even bank, a second even data bus, a first odd data bus connected with the odd bank, a second odd data bus, a common data bus. Even read data is outputted from the even bank in response to a first control signal, and odd read data is outputted from the odd bank in response to the first read control signal. A relaying unit is provided between a set of the first even and odd data buses and a set of the second even and odd data buses to receive the even read data on the first even data bus to output the even read data to the second even data bus in response to a second read control signal, and to receive the odd read data on the first odd data bus to output the odd read data to the second odd data bus in response to the second read control signal. An I/O circuit is provided between the common data bus and the set of the second even and odd data buses to receive the even read data from the second even data bus and the odd read data from the second odd data bus, and to output one of the even read data and the odd read data to the common data bus and then outputs the other to the common data bus, in response to a third read control signal.
Here, the semiconductor memory device may further include an external connection pad connected with the common data bus.
The I/O circuit may select one of the even read data and the odd read data based on a read selection control signal and output the selected data to the common data bus and then the other to the common data bus in response to the third read control signal.
In this case, the I/O circuit may output the selected data to the common data bus in response to a rising edge of the third read control signal and then the other to the common data bus in response to a falling edge of the third read control signal.
Also, the I/O circuit may receive write data from the common data bus in response to a first write control signal, the write data containing first write data and second write data subsequent to the first write data, and output one of the first and second write data as even write data to the second even data bus and the other as odd write data to the second odd data bus. The relaying unit may receive the even write data on the second even data bus to output to the first even data bus in response to a second write control signal, and receive the odd write data on the second odd data bus to output to the first odd data bus in response to the second write control signal. The even write data may be written in the even bank in response to a third write control signal, and the odd write data may be written in the odd bank in response to the third write control signal.
In this case, the I/O circuit may receive the first write data in response to a rising edge of the first write control signal, and the second write data in response to a falling edge of the first write control signal.
Also, the I/O circuit may select one of the first and second write data as the even write data based on a write selection control signal, and output the even write data to the second even data bus and the other as the odd write data to the second odd data bus.
Also, the semiconductor memory device may further include a control circuit which generates the first to third read control signals in response to an external clock signal. Also, the semiconductor memory device may further include the control circuit which generates the first to third write control signals in response to an external clock signal.
Also, the semiconductor memory device may further include a selection control circuit which generates the read selection control signal in response to a read start address and a CAS latency. Also, the semiconductor memory device may further include a selection control circuit which generates the write selection control signal in response to a write start address.
Also, the I/O circuit may include a selector section which selects one of the even read data and the odd read data based on the read selection control signal, and an output circuit which outputs the selected data to the common data bus and then the other to the common data bus in response to the third read control signal.
Also, the relaying unit may include a first tri-state buffer provided between the first even data bus and the second even data bus to receive the even read data on the first even data bus to output the even read data to the second even data bus in response to the second read control signal, and a second tri-state buffer provided between the fir

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