Semiconductor memory device with latch circuit and two...

Details Semiconductor memory device with latch circuit and two... Semiconductor memory device with latch circuit and two...

2002-12-31

2004-04-06

Auduong, Gene (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S050000, C365S154000, C365S171000

Reexamination Certificate

active

06717844

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, particularly to a semiconductor memory device including a latch circuit and two magneto-resistance elements.
2. Description of the Background Art
As a memory of low power consumption that can store data in a non-volatile manner, a MRAM (Magnetic Random Access Memory) employing a magneto-resistance element is now attracting attention.
FIG. 7
is a circuit block diagram showing a structure of a memory cell
51
in a conventional MRAM. Such a memory cell
51
is disclosed in, for example, U.S. Pat. No. 6,304,477.
Referring to
FIG. 7
, memory cell
51
is arranged at the crossing of a word line WL and a digit line DL, and a bit line pair BL, ZBL and a write bit line pair WBL, ZBL. Memory cell
51
includes P channel MOS transistors
52
and
53
, N channel MOS transistors
54
-
59
, and tunneling magneto-resistance elements
13
and
14
.
N channel MOS transistor
54
is connected between bit line BL and a node N
51
, and has its gate connected to word line WL. N channel MOS transistor
55
is connected between bit line ZBL and a node N
52
, and has its gate connected to word line WL. P channel MOS transistors
52
and
53
are connected between the line of power supply potential VDD and storage nodes N
51
and N
52
, respectively, and have their gates connected to nodes N
52
and N
51
, respectively. N channel MOS transistors
56
and
57
have their drains connected to storage nodes N
51
and N
52
, respectively, and their gates connected to storage nodes N
52
and N
51
, respectively. N channel MOS transistors
58
and
59
have their drains connected to the sources of N channel MOS transistors
56
and
57
, respectively, and their sources connected to the electrodes at the back face of tunneling magneto-resistance elements
60
and
61
, respectively. Both the gates of N channel MOS transistors
58
and
59
receive a signal EN. Program lines PL and ZPL at the front face of tunneling magneto-resistance elements
60
and
61
are connected to write bit lines WBL and ZWBL, respectively. Digit line DL is disposed in the proximity of the back face of tunneling magneto-resistance elements
60
and
61
.
When signal EN is driven to an H level (logical high) to render N channel MOS transistors
58
and
59
conductive and write bit lines WBL and ZWBL are pulled down to an L level (logical low), memory cell
51
attains a configuration identical to that of a memory cell of a SRAM (Static Random Access Memory). Storage nodes N
51
and N
52
store signals complementary to each other. These signals attain either one of an H level and an L level (binary). For example, storage nodes N
51
and N
52
retain an H level and an L level, respectively, to store data “1”. Storage nodes N
51
and N
52
retain an L level and an H level, respectively, to store data “0”. The write/read operation of signals of storage nodes N
51
and N
52
is carried out in a manner identical to that of a general SRAM.
In the case where signals of storage nodes N
51
and N
52
are to be written into tunneling magneto-resistance elements
60
and
61
, the signals of storage nodes N
51
and N
52
are first temporarily read out to an external source via bit line pair BL and ZBL. Then, a predetermined current is conducted to digit line DL and write bit lines WBL and ZWBL using a dedicated write circuit, whereby signals are written into tunneling magneto-resistance elements
60
and
61
. Each resistance value of tunneling magneto-resistance elements
60
and
61
depends upon the logic level of the written signal, and does not change even if power supply voltage VDD is cut off.
In the case where power supply potential VDD is cut off and applied again, the drive of signal EN to an H level causes write bit lines WBL and ZWBL to go low. Accordingly, the difference in the resistance between tunneling magneto-resistance elements
60
and
61
causes difference in the current drivability of pulling down storage nodes N
51
and N
52
to an L level. A signal of a logic level corresponding to the difference is read out to storage nodes N
1
and N
2
. Thus, this MRAM operates as a non-volatile memory.
In the case where the signals of storage nodes N
51
and N
52
are to be written into tunneling magneto-resistance elements
60
and
61
in a conventional MRAM, the signals of storage nodes N
51
and N
52
had to be first read out to an external source and then written using a dedicated write circuit and write bit lines WBL and ZWBL. There was a problem that signal writing is time-consuming. There was also the problem that the layout area is increased by the provision of the dedicated write circuit and write bit lines WBL and ZWBL.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide a semiconductor memory device of a small layout area that can write a signal in a storage node into a magneto-resistance element rapidly.
According to an aspect of the present invention, a semiconductor memory device includes first and second magneto-resistance elements. Each magneto-resistance element includes a magnetic material film, and a program line and an electrode formed at the front face and back face, respectively, of the magnetic material film. In response to a current exceeding a predetermined threshold current being conducted to the program line, the resistance value across the program line and electrode is altered. A binary signal is stored by that resistance value. The semiconductor memory device also includes a first inverter driven by a power supply voltage applied via the program line and electrode of the second magneto-resistance element to provide an inverted signal of the signal applied to a first storage node to a second storage node, a second inverter driven by a power supply voltage applied via the program line and electrode of the first magneto-resistance element to provide an inverted signal of the signal applied to the second storage node to the first storage node, and a first switching circuit responding to a write permit signal permitting writing of the signals in the first and second storage nodes to the first and second magneto-resistance elements to connect the program lines of the first and second magneto-resistance elements between the first and second storage nodes, respectively, and the line of a reference potential. Since the signal in a storage node is directly written into a magneto-resistance element, writing of a signal in a storage node to a magneto-resistance element can be carried out more rapidly than in the conventional case where the signal in the storage node is first read out to an external source and then written into a magneto-resistance element through a write circuit and write bit lines. Furthermore, the layout area can be reduced since it is not necessary to provide a write circuit and write bit lines.


REFERENCES:
patent: 6304477 (2001-10-01), Naji
patent: 6515895 (2003-02-01), Naji
patent: 2002-511631 (2002-04-01), None

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