Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2002-12-27
2004-02-10
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S185200
Reexamination Certificate
active
06690608
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device, which can internally produce data read timing with accuracy.
2. Description of the Background Art
In a static RAM (Random Access Memory), a word line drive pulse having a predetermined active period is produced in accordance with a change in address signal, and is applied to a word line. This word line drive pulse is produced with a sufficient margin in advance, so that correct data can be reliably read out even if a time required for data reading changes due to variations in process, change in ambient temperature and other(s). However, if the word line drive pulse has an extra margin, a read cycle time unnecessarily increases.
Japanese Patent Laying-Open No. 11-339476, for example, discloses a method, in which a read signal read from a dummy memory cell is supplied to a word line drive circuit or a row decoder for reducing a margin of the word line drive pulse to reduce a read cycle time.
In this conventional art, a read current is produced on a dummy bit line in accordance with data stored in the dummy cell. A potential change of the dummy bit line is detected to detect timing for reading out data from a normal memory cell, and equalizing of the bit line and deactivation of the selected word line are executed to aim minimization of the margin of the word line drive pulse.
In addition, a discharging time of the bit line is minimized for reducing current consumption.
In the prior art reference described above, a dummy bit line is connected to dummy cells, which are equal in number to normal memory cells connected to a normal bit line, so that the dummy bit line can have the same load as the normal bit line. However, when a dummy cell is selected, one dummy cell is driven to the selected state by a dummy cell driver, which is provided separately from a normal word line driver.
For increasing the integration degree of the memory cells, transistor sizes thereof are minimized. Therefore, when the bit line is discharged by the memory cell, only small potential change occurs on the normal bit line, so that the potential on the normal bit line changes only minutely. A differential type sense amplifier circuit having a high sensitivity is used for detecting such minute potential difference between normal bit lines in pair to determine data read from the memory cell, intending to speed up the data reading.
In the foregoing prior art, however, the dummy bit line is driven by one dummy cell so that change in potential on the dummy bit line, which transmits a signal read from the dummy cell, is substantially the same as change in potential on the normal bit line. Accordingly, the change in potential on the dummy bit line is a minute one. For detecting the potential change of the dummy bit line by a level detecting circuit such as an inverter, a long period is required before the potential on the dummy bit line lowers to or below the input threshold voltage of the inverter. Therefore, it becomes disadvantageously difficult to optimize the activation timing of the sense amplifier, activation timing of the bit line precharging and deactivation timing of a selected word line.
When one dummy cell is used to drive the dummy bit line, it is necessary to ensure a margin considering variation in sinking current of the selected dummy cell and variation in sinking current of the normal memory cell.
In general, as scaling is advanced to increase miniaturization of the elements, the degrees of variation in final geometrical feature and variation in dose of implanted impurity are increased so that variation in transistor characteristics becomes more significant. The degree of the variation in transistor characteristics further increases as a power supply voltage is lowered.
Accordingly, if one dummy cell is fixedly selected as disclosed in the foregoing prior art, accurate timing cannot be detected due to variations in transistor characteristics of the selected normal memory cell and the dummy cell. For example, if the transistor characteristics of the dummy cell may varies to a better characteristics to change the dummy bit line at higher speed, while transistor characteristics of a selected normal memory cell varies to a worse direction to slow down the change of the normal bit line, the deactivation of the word line and the activation of the sense amplifier are performed at excessively early timing so that a malfunction may occur.
For preventing the malfunction due to such variations in transistor characteristics of the dummy cell and normal memory cell, it is necessary to ensure a margin such that stable operations can be performed even under worst conditions. For these reasons, it is impossible to achieve the object of reducing the margin in the word line drive timing, and accordingly it becomes impossible to increase an operation speed and to reduce power consumption.
In ISSCC 2001, “Digest of Technical Papers”, pp. 168 and 169, Osada et al. discloses a structure, in which a plurality of dummy cells are simultaneously driven to the selected state to discharge the dummy bit line so that variation in discharging current of the dummy bit line can be leveled, to advance the timing of the read activation of the sense amplifier. In this structure, however, a dummy word line for selecting the dummy cells is provided separately from a normal word line for selecting the normal memory cell. The dummy cells connected to the dummy word line are fewer than the normal memory cells connected to the normal word line, and therefore, the dummy word line is driven to the selected state faster than the normal word line.
Thus, the dummy bit line is discharged at a timing faster than the timing of selecting the normal memory cell to discharge the normal bit line. Accordingly, the circuit design has to be made in consideration of difference in timing between driving of the dummy word line to the selected state and driving of the normal word line to the selected state, although a high margin is ensured for the variations in transistor characteristics of the memory cells by averaging the sinking current of the dummy bit line by the use of the plurality of dummy cells.
In particular, for another memory cell array having a different structure, in which a different number of normal memory cells are connected to one word line, or the number of normal memory cells connected to the normal bit line is changed, it is necessary to consider the difference in discharging speed between the normal bit line and the dummy bit line. Therefore, re-design is required for each structure of the memory cell array, taking into consideration the difference in activation timing between the dummy word line and the normal word line. In particular, for various bit/word configurations required in system LSIs and others, the optimum timing values must be set for each configuration, leading to a problem that an extremely long period is required for the design and development.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device, of which internal operation timing can be easily determined with accuracy.
Another object of the present invention is to provide a semiconductor memory device, in which an internal data read activation signal can be produced at an accurate timing regardless of variation in transistor characteristics.
A further object of the present invention is to provide a semiconductor memory device, in which an optimized internal data read activation signal can be easily produced even with a memory cell array configuration changed.
A semiconductor memory device according to the present invention includes a plurality of normal memory cells arranged in rows and columns, a plurality of dummy cells arranged in a plurality of columns, a plurality of dummy bit lines, arranged corresponding to the dummy cell columns, each connected to the dummy cells in the corresponding column, and a plurality of word lines, arranged correspondi
Nakase Yasunobu
Nii Koji
McDermott & Will & Emery
Nguyen Tuan T.
Renesas Technology Corp.
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