Semiconductor memory device with internal array transfer capabil

Details Semiconductor memory device with internal array transfer capabil Semiconductor memory device with internal array transfer capabil

1989-02-16

1989-11-07

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365203, 36518904, 340750, G11C 700, G11C 1140, G09G 114

Patent

active

048796859

ABSTRACT:
A semiconductor memory device includes, a plurality of word lines, a plurality of bit lines and a plurality of memory cells each connected between the word lines and the bit lines at each intersection of the word lines and bit lines. A plurality of sense amplifiers, each connected to each pair of bit lines, are for amplifying a difference in potential between each of the bit lines; a plurality of bit line reset circuits, each connected to each pair of the bit lines, the difference in potential being held during the read/write cycles. A transfer mode setting circuit is for optionally selecting a first word line and thereafter selecting a second word line, and for simultaneously reading out data in each memory cell connected to the first word line onto each bit line and thereafter simultaneously writing data on each bit line amplified by the sense amplifier into each corresponding memory cell connected to the second word line.

REFERENCES:
patent: 3898632 (1975-08-01), Spencer, Jr.
patent: 4162541 (1979-07-01), Hartke
patent: 4386421 (1983-05-01), Inagaki
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patent: 4412313 (1983-10-01), Ackland et al.
patent: 4429375 (1984-01-01), Kobayashi et al.
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patent: 4639890 (1987-01-01), Heilveil et al.
patent: 4644502 (1987-02-01), Kawashima
patent: 4661812 (1987-04-01), Ikeda
patent: 4688197 (1987-08-01), Novak

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