Semiconductor memory device with inhibiting test mode cancellati

Details Semiconductor memory device with inhibiting test mode cancellati Semiconductor memory device with inhibiting test mode cancellati

1990-04-27

1992-05-05

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

365195, 365222, 365233, G11C 700

Patent

active

051114330

ABSTRACT:
A semiconductor memory device comprises a test mode reset inhibiting circuit (22). The test mode reset inhibiting circuit (22) comprises a trigger signal generating circuit (31). When the semiconductor memory device is set in hidden fresh mode during a test mode period, a trigger signal (REFCT) is generated from the trigger signal generating circuit (31). As long as the trigger signal (REFCT) is generated, test mode reset is inhibited by the test mode reset inhibiting circuit (22).

REFERENCES:
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patent: 4507761 (1985-03-01), Graham
patent: 4547867 (1985-10-01), Reese et al.
patent: 4672583 (1987-06-01), Nakaizumi
patent: 4686456 (1987-08-01), Furuyama et al.
patent: 4692901 (1987-09-01), Kumanoya et al.
patent: 4758992 (1988-07-01), Taguchi
patent: 4811299 (1989-03-01), Miyazawa et al.
Nikkei Micro Device, No. 1, 1987, p. 146, "4MDRAM".

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