Semiconductor memory device with inhibiting test mode cancellati

Static information storage and retrieval – Read/write circuit – Testing

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365195, 365222, 365233, G11C 700

Patent

active

051114330

ABSTRACT:
A semiconductor memory device comprises a test mode reset inhibiting circuit (22). The test mode reset inhibiting circuit (22) comprises a trigger signal generating circuit (31). When the semiconductor memory device is set in hidden fresh mode during a test mode period, a trigger signal (REFCT) is generated from the trigger signal generating circuit (31). As long as the trigger signal (REFCT) is generated, test mode reset is inhibited by the test mode reset inhibiting circuit (22).

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