Static information storage and retrieval – Read/write circuit – Testing
Patent
1990-04-27
1992-05-05
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Testing
365195, 365222, 365233, G11C 700
Patent
active
051114330
ABSTRACT:
A semiconductor memory device comprises a test mode reset inhibiting circuit (22). The test mode reset inhibiting circuit (22) comprises a trigger signal generating circuit (31). When the semiconductor memory device is set in hidden fresh mode during a test mode period, a trigger signal (REFCT) is generated from the trigger signal generating circuit (31). As long as the trigger signal (REFCT) is generated, test mode reset is inhibited by the test mode reset inhibiting circuit (22).
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Nikkei Micro Device, No. 1, 1987, p. 146, "4MDRAM".
Mitsubishi Denki & Kabushiki Kaisha
Popek Joseph A.
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