Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2006-05-01
2008-08-19
Le, Vu A (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S185250
Reexamination Certificate
active
07414902
ABSTRACT:
A semiconductor memory device, including a plurality of programmable memory cells each one adapted to be brought into one among at least a first status and a second status, said plurality of memory cells including memory cells intended to store data, and means for accessing the memory cells for reading/modifying their status. At least one memory cell in said plurality is used as detector memory cell, and control means operatively associated with the at least one detector memory cell are provided, said control means being adapted to establishing a potential loss of the data stored in the memory cells of said plurality based on a detected first status of the at least one detector memory cell.
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European Search Report for EP 05 10 3557 dated Oct. 13, 2005.
Bedeschi Ferdinando
Resta Claudio
Graybeal Jackson Haley LLP
Jorgenson Lisa K.
Le Vu A
Santarelli Bryan A.
STMicroelectronics S.r.l.
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