Semiconductor memory device with increased capacitance and...

Details Semiconductor memory device with increased capacitance and... Semiconductor memory device with increased capacitance and...

2002-08-15

2004-03-23

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S303000, C257S305000, C257S308000, C257S309000, C257S307000

Reexamination Certificate

active

06710392

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices and particularly to semiconductor memory devices having a capacitor improved to obtain a sufficient and steady capacitance.
2. Description of the Background Art
Dynamic Random Access Memory (DRAM) has a structure formed of an integration of memory cells each having a single transistor and a single capacitor and it can be relatively readily miniaturized. However, recently as DRAM has more and more highly integrated a capacitor is required to be smaller in size and yet larger in capacitance. This can be achieved for example by increasing a surface area of the capacitor. Furthermore to ensure that the DRAM is reliable the capacitor is also required to have a capacitance free of significant variation.
A capacitor having a capacitance having a value large and free of significant variation is provided in a semiconductor memory device, as disclosed for example in Japanese Patent Laying-Open Nos. 5-304267 and 3-127859.
FIG. 13
is a cross section of a semiconductor memory device disclosed in Japanese Patent Laying-Open No. 5-304267.
With reference to
FIG. 13
, the conventional semiconductor memory device includes a silicon substrate
111
and an interlayer insulation film
112
formed on the substrate. Interlayer insulation film
112
is provided with a contact hole
113
reaching silicon substrate
111
. A polycrystalline silicon film
115
b
is provided to fill contact hole
113
and cover a surface of interlayer insulation film
112
. On interlayer insulation film
112
another polycrystalline silicon film
115
a
and another polycrystalline silicon film
115
c
are formed. Between polycrystalline silicon films
115
b
and
115
a
and between polycrystalline silicon films
115
b
and
115
c
, interlayer insulation film
112
has a surface
117
exposed. Polycrystalline silicon film
115
b
and
115
a
are divided by a trench for division
118
and so are polycrystalline silicon films
115
b
and
115
c
. A surface of trench
118
and polycrystalline silicon films
115
a
to
115
c
are covered by another polycrystalline silicon film
119
. Polycrystalline silicon films
115
a
to
115
c
and
119
form a bottom electrode
120
. On bottom electrode
120
a capacitance insulation film
121
is formed and thereon a top electrode
122
is formed of polycrystalline silicon.
FIG. 14
is a cross section showing a process of a method of fabricating the
FIG. 13
semiconductor memory device. With reference to
FIGS. 13 and 14
a conventional semiconductor memory device fabrication process will be described.
With reference to
FIG. 14
, on silicon substrate
111
interlayer insulation film
112
is formed. Interlayer insulation film
112
is provided with contact hole
113
reaching silicon substrate
111
. A first polycrystalline silicon film is formed to fill contact hole
113
and cover a surface of interlayer insulation film
112
. The trench for division
118
reaching a surface of interlayer insulation film
112
divides the first polycrystalline silicon film into a plurality of patterns to form the first polycrystalline silicon films
115
a
to
115
c
. The first polycrystalline silicon film
115
b
is formed through contact hole
113
onto an upper surface of interlayer insulation film
112
integrally. After the division the first polycrystalline silicon films
115
a
,
115
b
and
115
c
each has a surface provided with the second polycrystalline silicon film
119
and interlayer insulation film
112
exposed by trench
118
also has surface
117
provided with film
119
. The first polycrystalline silicon films
115
a
-
115
c
and the second polycrystalline silicon film
119
form bottom electrode
120
.
With reference to
FIG. 13
, capacitance insulation film
121
is formed on a surface of the second polycrystalline silicon film
119
configuring bottom electrode
120
and thereon top electrode
122
is formed of polycrystalline silicon.
As described above, the first polycrystalline silicon film is divided by the trench for division
118
, thereon the second polycrystalline silicon film
119
is formed, and they together serve as bottom electrode
120
. Bottom electrode
120
can thus contact capacitance insulation film
121
over an increased area. Such a semiconductor memory device can thus have a capacitor having a capacitance larger than a capacitor having a bottom electrode free of a trench for division. Furthermore, the trench for division
118
that is formed on interlayer insulation film
112
can constantly have a depth to surface
117
of interlayer insulation film
112
. Accordingly by controlling the second polycrystalline silicon film
119
in thickness the capacitor can have a capacitance free of significant variation.
As has been described above, in the conventional art, polycrystalline silicon is provided through contact hole
113
onto an upper surface of interlayer insulation film
112
integrally. Thus using a single material to form the first polycrystalline silicon film
115
b
integrally, however, is disadvantageous, as follows:
Typically, bottom electrode
120
is formed of polycrystalline or amorphous silicon doped with an impurity. If an impurity of a high concentration is used to dope the polycrystalline or amorphous silicon in contact hole
113
, however, the impurity diffuses into silicon substrate
111
. This impairs characteristics of a transistor of a memory cell. This is severely disadvantageous for DRAM, in particular, as the impurity diffused into the substrate impairs refresh function.
Furthermore, if the dopant impurity has a low concentration, a depletion layer disadvantageously results at a portion of bottom electrode
120
that contacts capacitance insulation film
121
. With reference to
FIG. 15
, bottom electrode
120
underlies capacitance insulation film
121
. Capacitance insulation film
121
underlies top electrode
122
. Bottom and top electrodes
120
and
122
are formed of polycrystalline silicon doped with phosphorus (P) serving as n dopant. Bottom electrode
120
is adapted to have a potential higher than top electrode
122
.
Bottom electrode
120
, doped with P serving as n dopant, internally has a large number of electrons
131
serving as carrier. Since electrons
131
move away from top electrode
122
having a relatively low potential, a depletion layer
120
a
free of carrier results in bottom electrode
120
at a portion adjacent to capacitance insulation film
121
. Thus between bottom and top electrodes
120
and
122
there exists two dielectrics, capacitance insulation film
121
and depletion layer
120
a
. The existence of depletion layer
120
a
results in a capacitor having a capacitance smaller than intended.
Furthermore in the conventional art the trench for division
118
provided in the first polycrystalline silicon film is formed on interlayer insulation film
112
to obtain trench
118
that has a predetermined depth reaching surface
117
of interlayer insulation film
112
. In this case, however, the first polycrystalline silicon films
115
a
and
115
c
consequently formed by trench
118
are situated on interlayer insulation film
112
and, as seen from a main surface
114
of silicon substrate
111
, the capacitor's projected area would be increased. This goes against a current demand for miniaturized capacitors.
SUMMARY OF THE INVENTION
The present invention has been made to overcome the above disadvantages and it contemplates a semiconductor memory device having a capacitor small in size and still sufficiently large in capacitance.
The present invention in one aspect provides a semiconductor memory device including: a semiconductor substrate having a main surface; an interlayer insulation film formed on the main surface of the semiconductor substrate and having a hole reaching the semiconductor substrate; a conductive layer filling the hole; a bottom electrode having a depression and electrically connected to the conductive layer; a dielectric film formed on the bott

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