Semiconductor memory device with increased bandwidth

Details Semiconductor memory device with increased bandwidth Semiconductor memory device with increased bandwidth

1996-12-27

1998-10-13

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Differential sensing

365205, 36523003, 365 63, G11C 702

Patent

active

058222618

ABSTRACT:
The present invention relates to a semiconductor memory device having a data bus line structure suitable for a high-speed burst read/write operation, and more particularly, to a semiconductor memory device capable of operating a high-speed burst read/write by displacing to pass a plurality of data buses over a cell array and sense amplifier array and pre-reading data of a plurality of sense amplifiers in a local data bus sense amplifier at the same time. A semiconductor memory device of the present invention comprises: a bit line sense amplifier array composed of K bit line sense amplifiers divided into 2.sup.n in a column direction; K/2.sup.n local data bus lines held in common on the bit line sense amplifier array of the same column direction and displaced to pass over a cell array and the bit line sense amplifier array; a sub column decoder connected to the bit line sense amplifier array so that one bit line sense amplifier per 2.sup.n bit line sense amplifiers on each bit line sense amplifier array can be connected with the local data bus lines; a switch means being so that the bit line sense amplifier selected by an output of the 2.sup.n sub decoders per each bit line sense amplifier array can be connected with the local data bus line; and K/2.sup.n data bus sense amplifiers connected to the K/2.sup.n local data lines to pre-read K/2.sup.n bit line sense amplifier data selected by the column decoder output.

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patent: 5666319 (1997-09-01), Okamura
patent: 5671188 (1997-09-01), Patel et al.

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