Semiconductor memory device with improved test efficiency

Details Semiconductor memory device with improved test efficiency Semiconductor memory device with improved test efficiency

1998-10-02

2000-07-18

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

365202, 36518904, 36523008, G11C 700

Patent

active

060916516

ABSTRACT:
I/O lines in an I/O gate-sense amplifier portion are arranged in the order of IOA, /IOB, IOB, and /IOA. As a result, the potentials of adjacent I/O lines are necessarily different at the time of writing/reading the same data to/from a plurality of memory cells during a multi-bit test. Therefore, a short-circuit fault caused between adjacent I/O lines can be detected at the same time.

REFERENCES:
patent: 4873669 (1989-10-01), Furutani et al.
patent: 5021998 (1991-06-01), Suzuki et al.
patent: 5241501 (1993-08-01), Tanaka
patent: 5600591 (1997-02-01), Takagi
patent: 5818792 (1998-10-01), Sasaki et al.

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