Semiconductor memory device with improved substrate arrangement

Details Semiconductor memory device with improved substrate arrangement Semiconductor memory device with improved substrate arrangement

1992-11-06

1995-06-20

Sikes, William L.

Static information storage and retrieval

Read/write circuit

Data refresh

36523008, 36523006, G11C 700, G11C 800

Patent

active

054266130

ABSTRACT:
A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

REFERENCES:
patent: 4354259 (1982-10-01), Ishimoto
patent: 4581718 (1986-04-01), Oishi
patent: 4680737 (1987-07-01), Oishi
patent: 4747082 (1988-05-01), Minato
patent: 4766570 (1988-08-01), Yamaguchi
patent: 4802135 (1989-01-01), Shinoda
patent: 4870620 (1989-09-01), Yamagata
patent: 4905198 (1990-02-01), Oishi
patent: 4914630 (1990-04-01), Fujishima

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