Semiconductor memory device with improved speed for reading data

Details Semiconductor memory device with improved speed for reading data Semiconductor memory device with improved speed for reading data

1994-03-21

1995-12-12

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365190, 365203, 365208, G11C 700

Patent

active

054756391

ABSTRACT:
Disclosed is a semiconductor memory device which operates based on voltages from a high voltage power source and a low voltage power source. A plurality of memory cells are formed in a memory cell array. Plural pairs of bit lines are connected to the memory cells to transfer data signals read from the memory cells. A sense amplifier, which has a pair of input terminals, amplifies the data signal. A level shifter is selectively connected to plural pairs of bit lines to shift the level of the data signal of a selected pair of bit lines to a level near the operation point of the sense amplifier, and supplies a resultant data signal to the sense amplifier. The level shifter includes a first transistor for receiving the data signal, and a plurality of second transistors connected between the first transistor and the low voltage power source. The first transistor has a first terminal to be supplied with the data signal, a second terminal and a control electrode for receiving a control signal for transferring the data signal to the sense amplifier. The second transistors are connected between the second terminal of the first transistor and the low voltage power source. The output of the second terminal of the first transistor is input to the input terminals of the sense amplifier.

REFERENCES:
patent: 4062000 (1977-12-01), Donnelly
patent: 4888737 (1989-12-01), Sato
patent: 5058072 (1991-10-01), Kashimura
patent: 5126974 (1992-06-01), Sasaki
patent: 5199000 (1993-03-01), Takahashi
patent: 5253137 (1993-10-01), Seevinck

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