Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-12-09
2004-03-02
Nguyen, Cuong (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S903000, C257S904000
Reexamination Certificate
active
06700166
ABSTRACT:
TITLE OF THE INVENTION
Semiconductor Memory Device with Improved Soft-Error Resistance
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor memory device. More particularly, the present invention relates to the memory cell structure of a static semiconductor memory device.
2. Description of the Background Art
As a memory cell used in a static random access memory (SRAM) (hereinafter, referred to as “SRAM memory cell”), an SRAM memory cell having a so-called “CMOS (Complementary Metal Oxide Semiconductor) structure” is conventionally known in the art. In the SRAM memory cell having the CMOS structure, a P-type MOS (Metal Oxide Semiconductor) transistor is used as a load transistor and N-type MOS transistors are used as a drive transistor and an access transistor.
FIG. 11
is a circuit diagram showing the structure of the conventional SRAM memory cell having the CMOS structure.
Referring to
FIG. 11
, conventional SRAM memory cell
100
includes a P-type MOS transistor PT
1
and an N-type MOS transistor NT
1
. P-type MOS transistor PT
1
is connected between a power supply node
110
for supplying a power supply potential VDD and a storage node NS. N-type MOS transistor NT
1
is connected between a ground node
115
for supplying a ground potential GND and storage node NS. Transistors PT
1
, NT
1
have their gates electrically coupled to a common gate line GL
1
, and form a single inverter.
SRAM memory cell
100
further includes a P-type MOS transistor PT
2
and an N-type MOS transistor NT
2
. P-type MOS transistor PT
2
is connected between power supply node
100
and a storage node /NS. N-type MOS transistor NT
2
is connected between storage node /NS and ground node
115
. Transistors PT
2
, NT
2
have their gates electrically coupled to a common gate line GL
2
, and form a single inverter.
Storage node NS is connected to gate line GL
2
, and storage node/NS is connected to gate line GL
1
. Such two cross-coupled inverters allow the potentials at storage nodes NS, /NS to be set to complementary levels. In other words, the potential at one of storage nodes NS, /NS is set to one of VDD level (hereinafter, sometimes referred to as “H level”) and GND level (hereinafter, sometimes referred to as “L level”), and the potential at the other storage node is set to the other level.
SRAM memory cell
100
further includes N-type MOS transistors AT
1
, AT
2
respectively connected between complementary bit lines BL, /BL and storage nodes NS, /NS. A gate line GLa
1
connected to the gate of transistor AT
1
and a gate line GLa
2
connected to the gate of transistor AT
2
are connected to a common word line WL.
In this way, an SRAM memory cell is implemented which uses P-type MOS transistors PT
1
, PT
2
as load transistors, N-type MOS transistors NT
1
, NT
2
as drive transistors, and N-type MOS transistors AT
1
, AT
2
as access transistors. In the SRAM memory cell of
FIG. 11
, data is written to or read from storage nodes NS, /NS through complementary bit lines BL, /BL during an active (H level) period of word line WL. During an inactive (L level) period of word line WL, data written to storage nodes NS, /NS are stably retained by the two cross-coupled inverters.
Note that, hereinafter, P-type MOS transistors PT
1
, PT
2
are sometimes referred to as load transistors PT
1
, PT
2
, N-type MOS transistors NT
1
, NT
2
are sometimes referred to as drive transistors NT
1
, NT
2
, and N-type MOS transistors AT
1
, AT
2
are sometimes referred to as access transistors AT
1
, AT
2
.
FIG. 12
shows one example of the two-dimensional layout of the SRAM memory cell in FIG.
11
.
FIG. 12
shows the layout to the level of a first metal wiring layer. The layout of further wiring layers is not shown in FIG.
12
.
Referring to
FIG. 12
, p-type wells
121
,
121
# and an n-type well
125
are formed at a semiconductor substrate. Drive transistor NT
1
and access transistor AT
1
, which are N-type MOS transistors, are provided on p-type well
121
. Load transistors PT
1
, PT
2
, which are P-type MOS transistors, are provided on n-type well
125
. Access transistor AT
2
and drive transistor NT
2
, which are N-type MOS transistors, are provided on p-type well
121
# which is separated from p-type well
121
.
More specifically, diffusion layer regions respectively corresponding to drive transistor NT
1
and access transistor AT
1
are formed at p-type well
121
. Diffusion layer regions respectively corresponding to load transistors PT
1
, PT
2
are formed at n-type well
125
. Diffusion layer regions corresponding to access transistor AT
2
and drive transistor NT
2
are formed at p-type well
121
#.
Power supply node
110
, ground node
115
, word lines WL, bit lines BL, /BL and storage nodes NS, /NS are formed in the first metal wiring layer or the like.
Gate lines GL
1
, GL
2
, GLa
1
, GLa
2
are formed from a polysilicon layer or the like. In order to implement the connection of
FIG. 11
, contacts
120
are provided as required between the first metal wiring layer, the diffusion layer regions and a gate line layer.
For example, regarding drive transistor NT
1
, a source portion of the diffusion layer region corresponding to drive transistor NT
1
is electrically coupled to ground node
115
via a contact
120
a
. A drain portion of the diffusion layer region corresponding to drive transistor NT
1
is electrically coupled to storage node NS via a contact
120
a
. Storage node NS is also electrically coupled to the diffusion layer region corresponding to access transistor AT
1
via contact
120
a.
Gate lines GLa
1
, GLa
2
respectively corresponding to access transistors AT
1
, AT
2
are electrically coupled via corresponding contacts
120
a
to word line WL formed in the first metal wiring layer. Gate line GL
1
extends so as to be coupled to the gates of drive transistor NT
1
and load transistor PT
1
. In a region above n-type well
125
, gate line GL
1
is electrically coupled to storage node /NS via a contact
120
b
. Contact
120
b
is provided as a contact capable of simultaneously connecting the gate, the diffusion layer and the first metal wiring layer (“shared contact”). Similarly, gate line GL
2
extends so as to be coupled to the gates of drive transistor NT
2
and load transistor PT
2
. In a region above n-type well
125
, gate line GL
2
is electrically coupled to storage node NS via a contact
120
b
. In general, such gate lines GL
1
, GL
2
, GLa
1
, GLa
2
have a silicide structure. In other words, in gate lines GL
1
, GL
2
, GLa
1
, GLa
2
, a silicide film, a thin metal silicide film (e.g., cobalt silicide), is formed on a polysilicon layer. This enables reduction in resistance of gate lines GL
1
, GL
2
, GLa
1
, GLa
2
.
However, recent progress of the semiconductor miniaturization technology increasingly reduces the size of the SRAM memory cells. This causes garbled data (inversion of storage data) due to external factors. One of the external factors is a so-called soft error. The soft error is caused by alpha rays that are emitted from a small amount of radioactive substance included in a package. The mechanism of generating a soft error in an SRAM memory cell will now be described with reference to FIG.
11
.
Referring back to
FIG. 11
, it is now assumed that, in the initial state, an L-level potential is stored in storage node NS, an H-level potential is stored in storage node /NS and word line WL is inactive at L level.
If alpha rays are emitted and electrons are excited in the drain portions of the N-type MOS transistors (AT
2
, NT
2
) coupled to storage node /NS storing H level, the potential at storage node /NS drops from H level. In such a case, the potential level at storage node /NS would normally restore to H level after a prescribed time because load transistor P
2
connected to storage node /NS is ON.
However, if the on-state resistance between the source and the drain of load transistor PT
2
is large, the reduced potential at storage node /NS may be propagated through gate line GL
1
before
McDermott & Will & Emery
Nguyen Cuong
Renesas Technology Corp.
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