Semiconductor memory device with improved output circuit

Details Semiconductor memory device with improved output circuit Semiconductor memory device with improved output circuit

1988-11-16

1990-03-13

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

365207, 365208, 36518905, 307445, 307446, G11C 1140, G11C 700

Patent

active

049087940

ABSTRACT:
A semiconductor memory device according to the present invention has a memory cell array and an output circuit provided in association with a pair of data lines which comprises a series combination of a main sense amplifier circuit and a first NOR gate, a series combination of an auxiliary sense amplifier circuit and a second NOR gate, and an output inverter circuit, and the two series combinations produces a data bit signal and the inverse thereof for driving the output inverter circuit, so that a time period consumed for a read-out operation is constant regardless of the logic level of a data bit read out from the memory cell.

REFERENCES:
patent: 4527081 (1985-07-01), Stewart
patent: 4604731 (1986-08-01), Konishi
patent: 4774690 (1988-09-01), Watanabe et al.
patent: 4807198 (1989-02-01), Flannagan et al.

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