Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-09-22
2002-06-25
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S063000, C365S230030
Reexamination Certificate
active
06411556
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device in which a redundancy determining circuit and the like are laid-out efficiently.
2. Description of the Background Art
An example of a conventional semiconductor memory device having redundant memory cells and a redundancy determining circuit will be described.
FIG. 15
is a block diagram representing a configuration of a conventional semiconductor memory device.
FIG. 16
shows a specific configuration of a memory block, in which a memory block
113
.
0
is shown as an example.
Mainly referring to
FIG. 15
, the conventional semiconductor memory device mainly includes a pair of memory mats MM in the left and right of the figure, a row related circuitry, a row control circuit, a column decoder
115
and a data input/output buffer
116
.
Memory mat MM is divided into memory blocks
113
.
0
,
113
.
1
, . . . ,
113
.
m
having a plurality of memory cells arranged in a matrix of rows and columns. Memory blocks
113
.
0
,
113
.
1
, . . . ,
113
.
m
respectively have normal memory blocks
113
.
0
a
,
113
.
1
a
, . . . ,
113
.
ma
and redundant memory blocks
113
.
0
b
,
113
.
1
b
, . . . ,
113
.
mb.
Mainly referring to
FIG. 16
, normal memory block
113
.
0
a
has a plurality of normal memory cells MC arranged in a matrix of rows and columns, and redundant memory block
113
.
0
b
has a plurality of redundant memory cells RMC arranged in a matrix of rows and columns. A normal word line WL is connected to gates of normal memory cells MC which are arranged in one same row. The normal word line WL is connected to a normal word driver
112
a
. A redundant word line RWL is connected to. gates of redundant memory cells RMC arranged in one same row, and the redundant word line RWL is connected to a redundant word driver
112
b
. The normal memory cells MC and redundant memory cells RMC arranged in the same row are connected to either one of a pair of bit lines BLP, which pair of bit lines BLP are connected to sense amplifier bands
114
.
0
and
114
.
1
on the upper and lower portions in the figure.
Mainly referring to
FIG. 15
, sense amplifier bands
114
.
0
,
114
.
1
, . . . ,
114
.
n
are arranged on opposing sides of the plurality of memory blocks
113
.
0
,
113
.
1
, . . . ,
113
.
m
, providing a shared sense amplifier scheme. The sense amplifier bands
114
.
0
,
114
.
1
, . . . ,
114
.
n
each has a sense amplifier sensing and amplifying data on a column of corresponding memory block when activated.
The row related circuitry is arranged along the longer side of memory mat MM in that area which is between the left and right memory mats MM, and performs operations related to selection of a row of memory cells. The row related circuitry has a row decoder
111
and a word driver
112
provided corresponding to each of memory blocks
113
.
0
,
113
.
1
, . . . ,
113
.
m
, and a redundancy determining circuit
101
, provided one for each of the pair of left and right memory blocks.
Each row decoder
111
includes a normal row decoder
111
a
selecting a normal word line WL in the normal memory block, and a redundant row decoder
111
b
selecting a redundant word line RWL in the redundant memory block. Each word driver
112
has a normal word driver
112
a
activating a selected normal word line WL, and a redundant word driver
112
b
activating a selected redundant word line RWL.
Redundancy determining circuit
101
includes, as shown in
FIG. 17
, a fuse
102
a
, an NMOS (N channel Metal Oxide Semiconductor) transistor
103
, and a redundancy determining signal generating circuit
104
. NMOS transistor
103
is connected between a line of ground potential (GND) and redundancy determining signal generating circuit
104
, and receives at its gate any of master address signals X
4
to X
19
. Between NMOS transistor
103
and redundancy determining signal generating circuit
104
, fuse
102
a
is connected. The plurality of fuses
102
a
are arranged in a column, constituting a fuse box
102
.
Mainly referring to
FIG. 15
, the row control circuit has a row predecoder
117
and a row address buffer
118
.
Row address buffer
118
outputs a row address signal in response to an external address signal. Row predecoder
117
outputs, based on the output of row address buffer
118
, master address signals X
4
to X
19
which are predecode signals for designating a word line WL.
Data input/output buffer
16
performs signal communication between data I/O pin and each memory block, under the control of column decoder
115
.
The master address signals X
4
to X
19
output from row predecoder
117
are applied to respective redundancy determining circuits
101
over a line extending by the length in the longitudinal direction of the row related circuitry. Further, the master address signals X
4
to X
19
are passed to a repeater
141
(
FIGS. 16
,
17
) through a line branching from the line extending in the lengthwise direction to be local address signals, which are applied to a normal row decoder
111
a.
The row selecting operation in the conventional semiconductor memory device will be described in the following.
Referring to
FIG. 15
, row address buffer
118
outputs a row address signal in response to an external address signal.
Row predecoder
117
outputs, based on the output of row address buffer
118
, master address signals X
4
to X
19
for designating a word line WL. The master address signals X
4
to X
19
are applied to redundancy determining circuit
101
, and local address signals from the master address signals X
4
to X
19
are applied to normal row decoder
111
a.
By the master address signals, a sense amplifier which is in contact with the selected memory block is disconnected from non-selected memory blocks, and an equalizing circuit, which is precharging the potential of the bit lines of the memory block at an intermediate potential VBL, is canceled.
Redundancy determining circuit
101
determines whether redundancy is to be used
ot to be used, based on master address signals X
4
to X
19
. When the redundancy is to be used, a normal word line WL including a defective memory cell MC in
FIG. 16
is set to a non-selected state, and a redundant word line RWL connected to redundant memory cell RMC to the selected state. The specific operation is as follows.
When there is a defective memory cell MC in the normal memory block, a fuse
102
corresponding to the row address of the defective memory cell MC is blown off (disconnected) by laser trimming (LT) or the like in advance.
Therefore, when the normal word line WL which is activated is not at an address to be replaced by the redundant word line RWL, the fuse
102
a
corresponding to that address is not blown off. Therefore, when the master address signals X
4
to X
19
corresponding to the address are input to redundancy determining circuit
101
, nodes A and B are short-circuited to GND through NMOS transistor
103
, and attain to L level.
When the normal word line WL to be activated is at the address which is to be replaced by the redundant word line RWL, the fuse
102
a
corresponding to the address has been blown off. Therefore, even when master address signals X
4
to X
19
corresponding to that address are input to redundancy determining circuit
101
, nodes A and B do not attain to the L level but are kept at the H level.
Dependent on the potential levels of nodes A and B, the redundancy determining signal is generated by redundancy determining signal generating circuit
104
. Based on the redundancy determining signal and the like, normal row decoder
111
a
sets the normal word line WL including the defective memory cell MC to non-selected state, and redundancy row decoder
111
b
selects the redundant word line RWL. Thus the normal word line WL including the defective memory cell MC is replaced by the redundant word line RWL, and the defect is repaired.
In the conventional semiconductor memory device, only one redundancy determin
Ho Hoai V.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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