Semiconductor memory device with improved indicator of state of

Details Semiconductor memory device with improved indicator of state of Semiconductor memory device with improved indicator of state of

1989-03-28

1991-01-08

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, G11C 700

Patent

active

049842056

ABSTRACT:
A semiconductor memory device having a redundant cell array and provided with an improved indicating circuit of the selection state of the redundant cell array is disclosed. The memory device comprises a tri-state type output circuit for generating read-out data from the selected memory cell at an output terminal, a detection circuit for generating a detection signal when the memory cell of the redundant cell array is selected and a control circuit for disenabling the output circuit thereby to make the output terminal at a high impedance state in response to the detection signal.

REFERENCES:
patent: 4392211 (1983-07-01), Nakano et al.
patent: 4463450 (1984-07-01), Haeusele

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