Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-05-18
2001-07-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230010, C365S231000
Reexamination Certificate
active
06262925
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having an error correction circuit (hereinafter abbreviated as ECC) incorporated therein.
2. Description of the Related Art
Some semiconductor memory devices have error correction circuits incorporated therein for correcting errors, when errors are found in data during reading of the data from a memory cell array. An ECC generally has functions of (1) detecting whether there is an error bit in the data, (2) determining the position of the error bit, and (3) correcting the error bit, for data of any bit length. While the function (1) is capable of detecting errors in data of any bit length by adding 1-bit parity bits, implementing the function of (2) and (3) requires a plurality of the parity bits for data of any bit length.
In general, correction of 1-bit error in a 32-bit data requires 6 parity bits, correction of 1-bit error in a 16-bit code word requires 5 parity bits and correction of 1-bit error in a 8-bit code word requires 4 parity bits. As for the error size that can be corrected in one step of correction, 1-bit correction is commonly employed when the ECC is used in a semiconductor memory device, in consideration of the number of parity bits required.
A semiconductor memory device having the built-in ECC, particularly one applied to a so-called masked ROM (read-only memory) that allows only to read out data once the device has been manufactured, is disclosed in Japanese Patent Laid-open Publication No. Hei 5-20896. This semiconductor memory device of the prior art will be described below with reference to FIG.
1
.
FIG. 1
is a block diagram of a masked ROM having ECCs that are capable of correcting 1-bit errors included in the 8-bit data.
In
FIG. 1
, a memory cell array (C
0
-C
7
)
1
consists of memory cell transistors comprising a plurality of MOS transistors arranged in a matrix. A parity cell array (P
0
-P
3
)
2
consists of parity cell (ECC cell) transistors comprising a plurality of MOS transistors arranged in a matrix. An address buffer circuit (AB)
3
receives an address signal as an input from the outside and outputs this signal to a pre-decode circuit
4
. Output of the pre-decode circuit (PD)
4
is input to Y select circuits (YC, YP)
5
a
,
5
b
and an X decoder circuit (X
0
)
6
. The Y select circuit
5
a
is a selector for data cells (memory cells), and the Y select circuit
5
b
is a selector for ECC cells. The pre-decode circuit
4
, the Y select circuits (YC, YP)
5
a
,
5
b
and the x decoder circuit (X
0
)
6
connect word select lines that pass channels of cell transistors in the memory call array (C
0
-C
7
)
1
and the parity cell array (P
0
-P
3
)
2
and DIGIT lines that connect to drains of cell transistors in the memory cell array (C
0
-C
7
)
1
and the parity cell array (P
0
-P
3
)
2
to sense amplifier circuits (S
0
-S
7
, E
0
-E
3
)
7
, in accordance with a combination of internal address signals that are output from the address buffer circuit (AB)
3
. The sense amplifier circuits (S
0
-S
7
, E
0
-E
3
)
7
detect information written on the memory call transistor and on the parity cell transistor that have been selected. An error detection circuit (ECC
1
)
8
and a syndrome decoder circuit (ECC
2
)
9
determine whether there is an error and locate an error bit, respectively, based on the information from the parity cell and the memory cell. Correction circuits (CR
0
~CR
7
)
10
correct the data of a bit indicated by a syndrome signal output from the syndrome decoder circuit (ECC
2
)
9
. An output buffer circuit (OB)
11
delivers output data (SC
0
~SC
7
) of the correction circuits (CR
0
~CR
7
)
10
to an external system.
The address buffer circuit (AB)
3
, the pre-decode circuit (PD)
4
, the Y select circuits (YC, YP)
5
a
,
5
b
, the X decoder circuit (X
0
)
6
, the sense amplifier circuits (S
0
-S
6
, E
0
-E
3
)
7
and the output buffer circuit (OB)
11
perform exactly the same functions as those of a semiconductor memory device commonly used, and description thereof will be omitted.
In the case of a masked ROM having a built-in ECC that is capable of correcting 1-bit error generated in 8-bit data, 8-bit memory cells in the memory cell array and 4-bit parity cells in the parity cell array are selected by the pre-decode circuit (PD), the Y select circuits (YC, YP) and the X decoder circuit (X
0
), so that 8-bit memory cell data and 4-bit parity cell data are read by the sense amplifier circuit.
“1” or “0” data are written in the memory cells and the parity cells by whether impurity ions are injected into the channel zone during diffusion or not. In case the memory cell transistors and the parity cell transistors are formed from NOR type N-channel transistors, P type ions (B ions or the like) are used as the impurity ions.
Description that follows assumes that the sense amplifier output is H (high) when the impurity ions are injected and is L (low) when the impurity ions are not injected.
In the case of a masked ROM, data to be written on the memory cell transistor is determined by a user of the masked ROM.
Data to be written in a parity cell, on the other hand, is determined by data of the memory cell transistor. When an address signal is input, for example, 8-bit data C
00
, C
01
, C
02
, C
03
, C
04
, C
05
, C
06
, C
07
are output from the memory cells C
0
, C
1
, C
2
, C
3
, C
4
, C
5
, C
6
, C
7
by the sense amplifier and, at the same time, P
00
, P
01
, P
02
, P
03
are output from the parity cells P
0
, P
1
, P
2
, P
3
that are selected by the address signals. At this time, data to be written in the parity cells P
0
, P
1
, P
2
, P
3
are determined so that the following equation 1 (determinant) is satisfied.
H·Vt=
0 (1)
where H; check matrix
V=[PO
0
PO
1
PO
2
PO
3
CO
0
CO
1
CO
2
CO
3
CO
4
CO
5
CO
6
CO
7
]
While any of several check matrixes shown in
FIG. 2
may used, the check matrix (
1
) in
FIG. 2
will be employed in the description that follows.
Such a case will be taken as an example as 8-bit output data from the sense amplifier is (C
00
, C
01
, C
02
, C
03
, C
04
, C
05
, C
06
, C
07
)=(00101100). By substituting the 8-bit data and the check matrix (
1
) in
FIG. 2
to the determinant shown in equation 1, the following equations 2 through 5 are obtained.
P
00
+
C
00
+
C
01
+
C
03
+
C
04
+
C
06
=
P
00
+
0
+
0
+
0
+
1
+
0
=0 (2)
P
01
+
C
00
+
C
02
+
C
03
+
C
05
+
C
06
=
P
01
+
0
+
1
+
0
+
1
+
0
=0 (3)
P
02
+
C
01
+
C
02
+
C
03
+
C
07
=
P
02
+
0
+
1
+
0
+
0
=0 (4)
P
03
+
C
04
+
C
05
+
C
06
+
C
07
=
P
03
+
1
+
1
+
0
+
0
=0 (5)
By calculating the above equations with mode
2
(binary), parity cell data of (P
00
, P
01
, P
02
, P
03
)=(1010) are obtained for the 8-bit data (C
00
, C
01
, C
02
, C
03
, C
04
, C
05
, C
06
, C
07
)=(00101100).
Logic circuits for the above equations (equations 2 through 5) are shown in FIG.
3
. The circuits shown in
FIG. 3
consist of XOR (exclusive logical sum) gates, and will be hereinafter called the error detection circuit. In
FIG. 3
, circuit group ECC
10
that includes XOR
100
,
101
,
102
,
103
,
104
represents the equation 2, circuit group ECC
11
that includes XOR
110
,
111
,
112
,
113
,
114
represents the equation 3, circuit group ECC
12
that includes XOR
100
,
121
,
122
,
123
represents the equation 4 and circuit group ECC
13
that includes XOR
130
,
131
,
132
,
133
represents the equation 5.
When there is no error in the data (P
00
, P
01
, P
02
, P
03
, C
00
, C
01
, C
02
, C
03
, C
04
, C
05
, C
06
, C
07
)=(101000101100) used as the example, outputs D
0
, D
1
, D
2
, D
3
of the error detection circuit are all “0”. When the memory cell or the parity cell has a fault and
Hutchins, Wheeler & Dittmar
Le Thong
NEC Corporation
Nelms David
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