Semiconductor memory device with improved defect elimination...

Details Semiconductor memory device with improved defect elimination... Semiconductor memory device with improved defect elimination...

2000-07-13

2002-05-21

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S203000, C365S230060

Reexamination Certificate

active

06392939

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device capable of efficiently detecting a defect during a burn-in test.
2. Description of the Background Art
Generally, device failures are caused roughly in the three periods of the initial failure period, the accidental failure period and the ware-out failure period in order of time.
In the initial failure period, defects which are caused during the device manufacturing process come to the surface as failures, and initial failures appear immediately after the start of use. The initial failure rate decreases rapidly with time.
Thereafter, the accidental failure period follows during which a low failure rate continues for a certain period.
Then, the device comes closer to its useful life and enters the ware-out failure period during which the failure rate increases rapidly.
Desirably, the device is used within the accidental failure period. This period corresponds to the useful life. In order to improve the device reliability, therefore, it is necessary that the accidental failure period with a low and constant failure rate continues long.
Meanwhile, in order to eliminate initial failures in advance, it is necessary to perform a screening process. In the screening process, an acceleration operation for aging is applied for a prescribed period so that any defect is made conspicuous, and a defective device found as a result is rejected. For a short term and effective screening process, such a screening test that reveals an initial failure in a short time is desirably performed.
Currently, a high temperature operation test (burn-in test) is generally conducted as one of the screening methods. The burn-in test can directly evaluate a dielectric film of an actual device, and the test reveals every defect cause including migration of an aluminum interconnection by applying high temperature and high electric field stresses. In recent years, the burn-in test as described above has been performed against a wafer before a semiconductor memory device is packaged, and a large number of chips have been tested at a time.
FIG. 7
is a circuit diagram showing a circuit configuration concerning a burn-in test in a conventional semiconductor memory device.
Referring to
FIG. 7
, a row decoder of the conventional semiconductor memory device includes a predecode circuit
26
a
, a main decode circuit
326
b
for driving even-numbered word lines WL
0
, WL
2
according to an output of predecode circuit
26
a
, row address signals RA
0
, RA
1
, a potential at a pad PD
0
for testing (hereinafter, referred to as test pad PD
0
) and a test signal TMRS, and a main decode circuit
326
c
for driving odd-numbered word lines WL
1
, WL
3
according to the output of predecode circuit
26
a
, row addresses RA
0
, RA
1
, a potential at a pad PD
1
for testing (hereinafter, referred to as test pad RA
1
) and test signal TMRS.
Predecode circuit
26
a
includes an AND circuit
52
for receiving row address signals /RA
2
, /RA
3
and outputting a signal X
4
, an AND circuit
54
for receiving row address signals /RA
4
, /RA
5
and outputting a signal X
8
, and an AND circuit
56
for receiving row address signals /RAG, /RA
7
and outputting a signal X
12
.
Main decode circuit
326
b
includes a composite gate circuit
362
for driving a signal RX
0
to the high level (hereinafter, referred to as the H level) when test signal TMRS is at the low level (hereinafter, referred to as the L level) and row address signals /RA
0
, /RA
1
are both at the H level and for driving signal RX
0
to the H level according to the potential at test pad PD
0
when test signal TMRS is at the H level.
Main decode circuit
326
b
further includes a composite gate circuit
364
for driving a signal RX
2
to the H level when test signal TMRS is at the L level and row address signals /RA
0
, /RA
1
are both at the H level and for driving signal RX
2
to the H level according to the potential at test pad PD
0
when test signal TMRS is at the H level.
Main decode circuit
326
b
further includes a composite gate circuit
368
for driving its output to the H level when test signal TMRS is at the L level and signals X
4
, X
8
, X
12
are all at the H level.
Main decode circuit
326
b
further includes a word driver
70
for activating word line WL
0
when signal RX
0
and the output of composite gate circuit
368
are at the H and L levels, respectively, and a word driver
72
for activating word line WL
2
when signal RX
2
and the output of composite circuit
368
are at the H and L levels, respectively.
Word driver
70
includes a P channel MOS transistor
74
and an N channel MOS transistor
76
which are connected in series between a node supplied with signal RX
0
and a ground node. The gates of N channel MOS transistor
76
and P channel MOS transistor
74
are supplied with the output of composite gate circuit
368
. A node for connecting P channel MOS transistor
74
and N channel MOS transistor
76
is connected to word line WL
0
.
Word driver
72
includes a P channel MOS transistor
78
and an N channel MOS transistor
80
which are connected in series between a node supplied with signal RX
2
and the ground node. The gates of P channel MOS transistor
78
and N channel MOS transistor
80
are supplied with the output of composite gate circuit
308
. A node for connecting P channel MOS transistor
78
and N channel MOS transistor
80
is connected to word line WL
2
.
Main decode circuit
326
c
includes a composite gate circuit
382
for driving a signal RX
1
to the H level when test signal TMRS is at the L level and row address signals RA
0
, /RA
1
are both at the H level and for driving signal RX
1
to the H level according to the potential at test pad PD
1
when test signal TMRS is at the H level.
Main decode circuit
326
c
further includes a composite gate circuit
384
for driving a signal RX
3
to the H level when test signal TMRS is at the L level and row address signals RA
0
, RA
1
are both at the H level and for driving signal RX
3
to the H level according to the potential at test pad RA
1
when test signal TMRS is at the H level.
Main decode circuit
326
c
further includes a composite gate circuit
388
for driving its output to the H level when test signal TMRS is at the L level and signals X
4
, X
8
, X
12
are all at the H level.
Main decode circuit
326
c
further includes a word driver
90
for activating word line WL
1
when signal RX
1
and the output of composite gate circuit
388
are at the H and L levels, respectively, and a word driver
92
for activating word line WL
3
when signal RX
3
and the output of composite gate circuit
388
are at the H and L levels, respectively.
Word driver
90
includes a P channel MOS transistor
94
and an N channel MOS transistor
96
which are connected in series between a node supplied with signal RX
1
and the ground node. The gates of N channel MOS transistor
96
and P channel MOS transistor
94
are supplied with the output of composite gate circuit
388
. A node for connecting P channel MOS transistor
74
and N channel MOS transistor
76
is connected to word line WL
1
.
Word driver
92
includes a P channel MOS transistor
98
and an N channel MOS transistor
100
which are connected in series between a node supplied with signal RX
3
and the ground node. The gates of P channel MOS transistor
98
and N channel MOS transistor
100
are supplied with the output of composite gate circuit
388
. A node for connecting P channel MOS transistor
98
and N channel MOS transistor
100
is connected to word line WL
3
.
In short, the conventional semiconductor memory device has a circuit configuration in which the word lines are divided into two groups of even-numbered and odd-numbered sides and the potential of each word line group can be controlled from two dedicated pads in order to detect a burn-in defect.
In the conventional semiconductor memory device, the circuit shown in
FIG. 7
is used to collective

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