Semiconductor memory device with high data access speed

Details Semiconductor memory device with high data access speed Semiconductor memory device with high data access speed

2000-03-31

2001-05-15

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700

Reexamination Certificate

active

06233183

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device with high data access speed for preventing selectively data delay in redundancy logic.
In general, dynamic random access memories (DRAMs) which are most widely used among semiconductor memory devices is widely used with the lowest value in the memory portion of the computer main memories and peripheral equipment. In particular, because the semiconductor memory devices are manufactured with microprocessing technique using high integration technology, probability to fail in the main parts of the memory device is high. In general, a technique is used to repair defects with spare elements. The technique is called as redundancy technology and logic embodying the redundancy technology is called as defect repair logic, redundancy logic or spare logic.
The portion of the memory device which is undoubtedly be repaired is a memory cell array. It is because the semiconductor memory chip can not used when any one of memory cells in the memory cell array is defective. The memory device with matrix type includes redundancy logic where spare memory cells are provided in row or in column of the memory cell array and when the defect in any memory cell of memory cell array, the defective memory cell is substituted by the space memory cell. The spare logic is a row redundancy logic and a column redundancy logic.
In general, the memory devices, typical DRAMs, carry out the read and write operation for reading/writing data from/in the memory cell array with commands combined with address. Because the access speed is an essential factor for estimating performance of the memory device, the memory device with high access speed has a superior competitiveness.
However, the redundancy logic circuit has a problem to delay access speed. So as to understand the problem, the operation of typical DRAM will be first described hereinafter.
It uses address multiplexing method that a row address and a column address are provided with time delay in the DRAM. When a row address strobe (RAS) signal is activated, the row address is received and when a column address strobe (CAS) signal is activated, the column address is received so that finally, the selected memory cell is accessed. In DRAM operation, the activation speed of the RAS signal is more important than that of the CAS signal. It is because of DRAMs, synchronous dynamic random access memories (SDRAMs) operates with burst mode that the consecutive CAS activation following one RAS activation so that the data access speed determines the performance of DRAMs.
In particular, SDRAM outputs data in syncronization with clock and generates an external address signal or an internal address signal at a toggle edge of every clock to select a column selection signal. Accordingly, the speed to select the column selection signal determines data access speed with CAS activation.
FIG. 1
shows a block diagram of a DRAM in the prior art. The prior redundancy circuit includes a plurality of address input terminals
10
for receiving an external column address signal Y-add bit by bit; a plurality of address input buffers
20
for converting the external column address signal Y-add through the address input terminals
10
into an internal column address signal bit by bit, each of the address input buffers
20
being corresponding to each of the address input terminals; an address predecoder
30
for predecoding the internal column address signal from the address input buffers
20
to generate global column address signals GAYij; a column redundancy fuse array
40
for receiving the global column address signals GAYij and detecting whether they are redundancy addresses to generate a spare detection signal SD; a redundancy selector
50
for selectively generating a normal column enable signal NCE or a spare column enable signal SCE in accordance with the spare detection signal SD from the column redundancy fuse array
40
; an address block repeater for receiving the global column address signals GAYij and the normal column enable signal NCE to generate column address signals BAYij; a column main decoder
70
for receiving the column address signals BAYij from the address block repeater
60
and decoding them to generate column selection signals Yi<n>; and a spare column decoder
80
for receiving the spare column enable signal SCE from the redundancy selector
50
to generate spare column selection signals SYi.
FIG. 2
shows a circuit diagram of the address block repeater in FIG.
1
. The address block repeater
60
includes a first delay portion
61
to a fourth delay portion
64
for respectively receiving the predecoded address signals GAY
01
<
0
>-GAY
01
<
3
> and for delaying them for a selected time which is a desired minimum time for detecting the redundancy; a plurality of a first to a fourth AND logic portions
65
-
68
for receiving the normal column enable signal NCE and output signals of the delay portions
61
-
64
to generate column address signals BAY
01
<
0
>-BAY<
3
>.
The delay portions include a plurality of inverters IV
1
-IV
4
, IV
5
-IV
8
, IV
9
-IV
12
and IV
13
-IV
16
connected in series and the AND logic portions include NAND gate NA
1
-NA
4
and inverter IV
17
-IV
20
.
FIG. 3
shows a circuit diagram of the column main decoder in FIG.
1
. The column main decoder
70
receives the column address signals BAY<
0
>-BAY<
3
> from the address block repeater
60
of FIG.
2
and decodes them to activate any one of the column selection signals Yi<
0
>-Yi<
3
>.
FIG. 4
shows a circuit diagram of the column redundancy fuse array in FIG.
1
. The column redundancy fuse array includes a PMOS transistor MP
1
for precharging the potential of a defect detection node Nd
1
with a power voltage Vdd by a precharge signal pcg which is applied to a gate thereof; a plurality of NMOS transistors MN
1
-MN
12
which receive the global column address signals GAY
01
<
0
>-GAY
45
<
3
> from the address predecoder
30
to drop the potential of the node Nd
1
to a ground terminal Vss; a plurality of fuses F
1
-F
12
connected to the defect detection node Nd
1
and drains of the NMOS transistors MN
1
-MN
12
; a plurality of inverters IV
1
-IV
2
connected to the defect detection node Nd
1
, for generating the spare detection signal SD.
If the global address signals corresponding to the defect cells are GAY
01
<
0
>, GAY
23
<
0
> and GAY
45
<
0
>, so as to detect the global address signal GAY
01
<
0
>, GAY
23
<
0
> and GAY
45
<
0
>, the fuses F
1
, F
5
, F
9
connected to the NMOS transistors MN
1
, MN
5
and MN
9
where the global address signals are applied to gates become blown by using laser. At this time, if other addresses GAY
01
<
1
>-GAY
01
<
3
>, GAY
23
<
1
>-GAY
23
<
3
>, GAY
45
<
1
>-GAY
45
<
3
> except for the above redundancy address GAY
01
<
0
>, GAY
23
<
0
> and GAY
45
<
0
> are received from the predecoder
30
, potential of the defect detection node Nd
1
becomes at a ground level Vss by the non-blown fuses F
2
-F
4
, F
6
-F
8
and F
10
-F
12
so that it becomes at logic low level. Finally, the column redundancy fuse array
40
generates the spare detection signal SD of logic low level.
On the other hand, if the redundancy addresses GAY
01
<
0
>, GAY
23
<
0
> or GAY
45
<
0
> are received, because the fuses F
1
, F
5
, and F
9
corresponding to the redundancy address are already blown, the defect detection node Nd
1
maintains its initial logic high level. Finally, the redundancy fuse array
40
generates the spare detection signal SD of logic high level.
FIG. 5
shows a circuit diagram of the redundancy selector and the spare column decoder in FIG.
1
. The redundancy selector
50
which receives the spare detection signal SD from the column redundancy fuse array
40
to generate the normal column enable signal NCE and a spare column enable signal SCE, includes inverters IV
23
and IV
25
for inverting the spar

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