Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
1999-12-06
2001-05-01
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S190000, C365S196000, C365S207000, C365S208000, C365S230030, C365S230060, C365S202000
Reexamination Certificate
active
06226208
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly a semiconductor memory device provided with hierarchical control signal lines.
2. Description of the Background Art
In a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), a large number of sense amplifiers for amplifying minute potential differences occurring on bit line pairs are arranged in a straight line. Each sense amplifier includes a P-channel sense amplifier for raising the voltage on one of the paired bit lines to a power supply voltage, and an N-channel MOS transistor for lowering the voltage on the other bit line to a ground voltage. For operating the sense amplifier, it is required to provide a sense signal for driving the P-channel sense amplifier as well as a sense signal for driving the N-channel sense amplifier. Therefore, a sense signal line for driving the P-channel sense amplifiers and a sense signal line for driving the N-channel sense amplifiers are arranged along the large number of sense amplifiers arranged in a line. These P-channel sense amplifiers are commonly connected to the sense signal line, and all operate simultaneously in response to the sense signal. The N-channel sense amplifiers are commonly connected to the other sense signal line, and all operate simultaneously in response to the sense signal.
As described above, the conventional device is provided with the two sense signal lines arranged along the large number of sense amplifiers arranged in a line so that the device suffers from increase in layout area.
With increase in memory capacity, it may be contemplated to employ a hierarchical structure for the control signal lines, similarly to word lines and bit lines. For employing the hierarchical structure in which the control signal is hierarchically divided into a main signal line and many sub-signal lines, the length of main signal line must be increased with increase in memory capacity. Increase in length of the main signal line results in a problem that signal delay increases with increase in distance to the sub-signal line from a source of the control signal.
SUMMARY OF THE INVENTION
An object of the invention is to provide a semiconductor memory device, of which layout area can be reduced.
Another object of the invention is to provide a semiconductor memory device, in which signal delays on hierarchical control signal lines can be reduced.
According to an aspect of the invention, a semiconductor memory device includes a memory cell array divided into a plurality of blocks. The plurality of blocks are arranged in rows and columns. The memory cell array includes a plurality of sense signal lines for transmitting a main sense signal. Each of the sense signal lines is arranged in the blocks arranged in the single row. Each of the blocks includes a sub-array, a plurality of sense amplifiers and a sub-sense signal generator. The subarray includes a plurality of memory cells arranged in rows and columns, a plurality of first word lines arranged along the row, and a plurality of bit line pairs arranged along the column. The plurality of sense amplifiers correspond to the plurality of bit line pairs, respectively. Each of the sense amplifiers is connected to the corresponding bit line pair, and includes a P-channel sense amplifier responsive to a first sub-sense signal, and an N-channel sense amplifier responsive to a second sub-sense signal. The sub-sense signal generator is connected to corresponding one among the sense signal lines, and is responsive to the main sense signal to generate the first and second sub-sense signals.
In the above semiconductor memory device, only one sense signal line is arranged in the blocks arranged in the single row. Therefore, a layout area required for the sense signal lines can be reduced.
According to another aspect of the invention, a semiconductor memory device includes a memory cell array divided into a plurality of blocks. The plurality of blocks are arranged in rows and columns. The memory cell array includes a plurality of control signal lines for transmitting a main control signal. Each of the control signal lines is arranged in the blocks arranged in the single row. Each of the blocks includes a sub-array, a function circuit and a sub-control signal generator. The sub-array includes a plurality of memory cells arranged in rows and columns, a plurality of word lines arranged along the row and a plurality of bit line pairs arranged along the column. The function circuit is responsive to a sub-control signal to perform an operation necessary for writing/reading data into/from the memory cell. The sub-control signal generator is connected to the control signal line, and is responsive to the main control signal to generate the sub-control signal. The sub-control signal generator includes a first inverter for receiving the main control signal, and a second inverter for supplying the sub-control signal in response to the output signal of the first inverter. The first inverter is formed of a transistor having a smaller size than a transistor forming the second inverter.
In the semiconductor memory device described above, since the transistor forming the first inverter has a smaller size than the transistor forming the second transistor, it is possible to suppress increase in total parasitic capacity of the control signal lines so that the sub-control signal can be produced without a significant delay even in a position remote from the source of the main control signal.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5652730 (1997-07-01), Kono et al.
patent: 3-266297 (1991-11-01), None
Ikeda Yutaka
Nakai Jun
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Tran Andrew Q.
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