Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2000-04-27
2003-03-18
Hudspeth, David (Department: 2651)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S152000, C711S170000
Reexamination Certificate
active
06535965
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, in particular, to a semiconductor memory device having a burst write mode.
2. Description of the Related Art
In recent years, the performance of parts of computers and other information processing systems has greatly improved. Thus, for semiconductor memory device such as SDRAM (Synchronous Dynamic Random Access Memory), for example, a higher operating speed and an improved data transfer rate, including a multi-bit input/output configuration, are sought.
Specifically, a double data rate (DDR) has come to be employed as a means for increasing the operating speed, in which the clock frequency is increased or data are input or output at both the leading edge and the trailing edge of the clock without increasing the clock frequency.
With the increase in transfer rate, the operation requirement in the circuits cannot be met by writing or reading the data bit by bit. Burst processing (burst read and burst write) for collectively processing several bits of serially input data is required.
At the time of write operation for burst processing (burst write mode), the actual write operation into the core is required to be held before all the data are ready (until the write data for the burst length is prepared). A higher speed of the processing in burst write mode is desired.
The related art and the problem points thereof will be described in detail with reference to the accompanying drawings.
SUMMARY OF THE INVENTION
An object of the present invention is to improve the data transfer rate by increasing the speed of the masking process in the burst write mode. Another object of the invention is to set the burst length without inputting a mode register set command.
According to the present invention, there is provided a semiconductor memory device having a burst write mode wherein predetermined plural command signals are input through a plurality of command pads, and a mask control operation is performed in the burst write mode in response to the command signals.
The command signals may be a plurality of write enable signals input in parallel through the plurality of the command pads and the plurality of the write enable signals may be decoded thereby to mask an arbitrary one of a plurality of continuous write data in the burst write mode.
Further, according to the present invention, there is provided a semiconductor memory device having a burst write mode, wherein mask data are input in parallel through a plurality of mask data pads, and a mask control operation is performed in the burst write mode by the plurality of the mask data.
The number of the mask data pads may be smaller than the number of bits of the burst length in the burst write mode, and the mask control operation for a plurality of bits of the write data may be performed by the mask data input through one of the mask data pads.
The mask control operation in the burst write mode may be performed in such a manner that the mask data corresponding to a plurality of the write data are completely fetched before the plurality of the write data of the burst length are fetched completely.
In addition, according to the present invention, there is provided a semiconductor memory device having a burst write mode, wherein a plurality of input data are provided in serial to a data terminal and a plurality of mask data are provided, comprising a mask data input circuit for receiving the plurality of mask data before the last input data of the plurality of input data is provided to the data terminal.
The semiconductor memory device may further comprise a plurality of write enable signal terminals for receiving a plurality of write enable signals as the plurality of mask data, wherein the mask data input circuit may be coupled to the plurality of write enable signal terminals.
The semiconductor memory device may further comprise a plurality of mask data terminals for receiving the plurality of mask data, wherein the mask data input circuit may be coupled to the plurality of mask data terminals. The number of the mask data terminals may be the same as that of the mask data. The number of the mask data terminals may be less than that of the mask data.
The semiconductor memory device may further comprise a plurality of address signal terminals for receiving the plurality of mask data, wherein the mask data input circuit may be coupled to the plurality of address signal terminals.
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Ikeda Hitoshi
Sato Kotoku
Sato Yasuharu
Suzuki Takaaki
Uchida Toshiya
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Hudspeth David
Tzeng Fred F.
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