Semiconductor memory device with error correction

Details Semiconductor memory device with error correction Semiconductor memory device with error correction

2008-09-30

2011-12-13

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

Reexamination Certificate

active

08078923

ABSTRACT:
This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.

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Office Action issued Jan. 14, 2011 in Korea Application No. 10-2009-7017089 (With English Translation).

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